RICHARD CRAIG KISCADEN
Pilots at 11 St, Rochester, MN
License number
Minnesota A4039151
Issued Date
Jun 2015
Expiration Date
Jun 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
724 11Th St SW, Rochester, MN 55902
Professional information
Address Translation With Storage Protection
US Patent:
4093986, Jun 6, 1978
Filed:
Dec 27, 1976
Appl. No.:
5/754392
Inventors:
Ronald Eugene Bodner - Rochester MN
Thomas Lee Crooks - Rochester MN
Richard Craig Kiscaden - Rochester MN
Thomas Lee Crooks - Rochester MN
Richard Craig Kiscaden - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300, G06F 920
US Classification:
364200
Abstract:
Storage protection is provided in a computer system having address translation by loading address translate registers with valid translated addresses and with special addresses. A circuit for generating a storage exception signal is connected to receive all addresses from the translate registers which are addressed by the main storage address and generates a storage exception signal in response to detecting a special address. The address translation mode is provided for both a main storage processor and a control processor with a separate address translate control register for each processor. Address translation is automatically selected based upon interrupt level. Address translation registers are also provided for I/O operations and are controlled independently from and can be in parallel with the task address translation registers.
Asymmetrical Multiprocessor System
US Patent:
4077060, Feb 28, 1978
Filed:
Dec 27, 1976
Appl. No.:
5/754390
Inventors:
Ronald Eugene Bodner - Rochester MN
Richard Craig Kiscaden - Rochester MN
Richard Craig Kiscaden - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1516, G06F 1520
US Classification:
364200
Abstract:
An asymmetrical multiprocessor system has a main storage or macroprocessor connected under control of a microprocessor for initiation and termination of operation of the macroprocessor. The macroprocessor after being started by the microprocessor runs until a check condition in the macroprocessor occurs, a non-executable operation code (OP code) in the macroprocessor is encountered, or the microprocessor wants control. When the macroprocessor stops the microprocessor is interrupted. The interrupt routine handles the condition causing the interrupt and restarts the macroprocessor. Non-executable OP codes include supervisor call and invalid OP codes. I/O operations are handled by the supervisor call instruction.