RICHARD BARTH, MD
Radiology at Pasteur Dr, Palo Alto, CA

6708248, Mar 16, 2004

Dec 8, 1999

09/457155

Frederick Abbott Ware - Los Altos Hills CA
Craig E. Hampel - San Jose CA
Richard M. Barth - Palo Alto CA
Donald C. Stark - Los Altos CA
Abhijit Mukund Abhyankar - Sunnyvale CA
Catherine Yuhjung Chen - Milpitas CA
Thomas J. Sheffler - San Francisco CA
Ely K. Tsern - Los Altos CA
Steven Cameron Woo - Saratoga CA

Rambus Inc. - Los Altos CA

G06F 1200

711104, 711147, 711154, 711167, 710 28, 710 33

A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively controllable group to transmit or receive high bandwidth data.

RE37409, Oct 16, 2001

Apr 26, 2000

9/559836

Richard M. Barth - Palo Alto CA
Donald C. Stark - Los Altos Hills CA
Lawrence Lai - San Jose CA
Wayne S. Richardson - Saratoga CA

Rambus Inc. - Los Altos CA

G11C 1300

36523003

A memory and method of operation is disclosed. In one embodiment, the memory includes a group of memory cells divided into a plurality of subgroups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a subgroup and is coupled to the memory cells in the row of the corresponding subgroup. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit (s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.

6209071, Mar 27, 2001

May 7, 1996

8/648300

Richard Maurice Barth - Palo Alto CA
Mark Alan Horowitz - Palo Alto CA
Craig Edward Hampel - San Jose CA
Frederick Abbot Ware - Los Altos Hills CA

Rambus Inc. - Mountain View CA

G06F13/14

711167

A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

5748914, May 5, 1998

Oct 19, 1995

8/545292

Richard Maurice Barth - Palo Alto CA
Frederick Abbot Ware - Los Altos Hills CA
John Bradly Dillon - Palo Alto CA
Donald Charles Stark - Woodside CA
Craig Edward Hampel - San Jose CA
Matthew Murdy Griffin - Mountain View CA

Rambus, Inc. - Mountain View CA

G06F 700

395285

A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

8458385, Jun 4, 2013

Jun 27, 2012

13/535228

Mark A. Horowitz - Menlo Park CA, US
Richard M. Barth - Palo Alto CA, US
Craig E. Hampel - San Jose CA, US
Alfredo Moncayo - Redwood City CA, US
Kevin S. Donnelly - Los Altos CA, US
Jared L. Zerbe - Woodside CA, US

Rambus Inc. - Sunnyvale CA

G06F 13/00, G05F 1/10

710104, 326 80, 327535, 365189011

A chip includes a receiver circuit that uses a reference voltage to receive a data signal such that a logic level of the received data signal is determined using the reference voltage, and a register to store a value that represents an adjustment to the reference voltage.

2012005, Mar 8, 2012

Oct 5, 2011

13/253911

Ely K. Tsern - Los Altos CA, US
Richard M. Barth - Palo Alto CA, US
Craig E. Hampel - San Jose CA, US
Donald C. Stark - Los Altos CA, US

G11C 8/18

36523315

A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

7986584, Jul 26, 2011

Oct 29, 2009

12/608209

Ely K. Tsern - Los Altos CA, US
Richard M. Barth - Palo Alto CA, US
Craig E. Hampel - San Jose CA, US
Donald C. Stark - Los Altos CA, US

Rambus Inc. - Sunnyvale CA

G11C 8/18

36523315, 365227, 365219

A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

5430676, Jul 4, 1995

Feb 25, 1994

8/202290

Frederick A. Ware - Los Altos Hills CA
John B. Dillon - Palo Alto CA
Richard M. Barth - Palo Alto CA
Billy W. Garrett - Mountain View CA
John G. Atwood - San Jose CA
Michael P. Farmwald - Portola Valley CA

Rambus, Inc. - Mountain View CA

G06F 1200

36518902

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

7546390, Jun 9, 2009

Oct 30, 2007

11/929980

Mark A. Horowitz - Menlo Park CA, US
Richard M. Barth - Palo Alto CA, US
Craig E. Hampel - San Jose CA, US
Alfredo Moncayo - Redwood City CA, US
Kevin S. Donnelly - Los Altos CA, US
Jared L. Zerbe - Woodside CA, US

Rambus, Inc. - Los Altos CA

G06F 13/00, G06F 12/00

710 16, 710305, 711170, 36518905

An integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device. The value is representative of an equalization co-efficient setting that compensates for signals present on an external signal line. The signals present on the external signal line comprise one selected from residual signals and cross coupled signals.