REBECCA ELIZABETH HEBDA
Pilots at 144 Ter, Portland, OR

License number
Oregon C1039750
Category
Airmen
Address
Address
15320 SW 144Th Ter, Portland, OR 97224

Personal information

See more information about REBECCA ELIZABETH HEBDA at radaris.com
Name
Address
Phone
Rebecca E Hebda, age 51
11480 Hazelwood Loop, Portland, OR 97223
(503) 524-6800
Rebecca E Hebda, age 51
15320 144Th Ave, Portland, OR 97224
(503) 524-6800
(503) 625-9614
Rebecca E Hebda, age 51
17986 Cereghino Ln, Sherwood, OR 97140
(503) 625-9614
Rebecca E Hebda
15320 SW 144Th Ter, Portland, OR 97224
(503) 524-6800
Rebecca Hebda
11480 SW Hazelwood Loop, Portland, OR 97223
(503) 524-6800

Professional information

Rebecca Hebda Photo 1

Senior Design Engineer At Intel Corporation

Position:
Senior Design Engineer at Intel Corporation
Location:
Portland, Oregon Area
Industry:
Semiconductors
Work:
Intel Corporation - Senior Design Engineer


Rebecca Hebda Photo 2

Apparatus Having A Micro-Instruction Queue, A Micro-Instruction Pointer Programmable Logic Array And A Micro-Operation Read Only Memory And Method For Use Thereof

US Patent:
7519799, Apr 14, 2009
Filed:
Nov 18, 2003
Appl. No.:
10/714674
Inventors:
Rebecca E. Hebda - Tigard OR, US
Jourdan J. Stephan - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/38, G06F 9/00, G06F 9/44, G06F 15/00
US Classification:
712245, 712211
Abstract:
Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single memory. A processor including multiple programmable logic arrays (PLAs); an instruction pointer queue coupled to the multiple PLAs; and an instruction pointer sequencing logic/predictor component coupled to the instruction pointer queue. The processor further includes a micro-operation cache coupled to the instruction pointer sequencing logic/predictor component; a micro-operation memory coupled to the micro-operation cache; and a trace pipe (TPIPE) coupled to the micro-operation cache and the instruction pointer queue.