RANDY LEE BAILEY
Pilots at Chippendale Dr, Fort Collins, CO

6834364, Dec 21, 2004

Apr 19, 2001

09/838766

Brad D Reak - Loveland CO
Randy L Bailey - Ft Collins CO
John M Freeseman - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

G06F 11273

714 45, 714718, 714732

A trigger signal for a memory tester uses a (breakpoint) trigger qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed before becoming a system trigger signal that can be used to trigger a ‘scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. To provide stable waveforms for the sweeping of the voltage thresholds and sample timing offset the memory tester records the addresses for a target sequence of transmit vectors issued during an initial pass through the test program subsequent to the occurrence of the trigger. These addresses are exchanged for the instructions themselves, which are then altered to remove branching, and stored in a reserved portion of the memory they came from. Once the altered target sequence is stored the desired information is produced by restarting the entire test program and letting it run exactly as before down to the trigger. Now when the trigger occurs further transmit vectors are issued from the memorized target sequence, rather than from the live algorithm, and a combination of voltage thresholds and the sample timing offset are switched into place.

6671844, Dec 30, 2003

Oct 2, 2000

09/677202

John M Freeseman - Fort Collins CO
Randy L Bailey - Ft Collins CO
Edmundo De La Puente - Cupertino CA

Agilent Technologies, Inc. - Palo Alto CA

G01R 3128

714736, 714742

A memory tester supports testing of multiple DUTs of the same type at a test site. The tester can be instructed to replicate the segments of the test vectors needed to test one DUT on the channels for the other DUTs. This produces patterns of transmit and receive vectors that are n-many DUTs wide. Conditional branching within the test program in response to conditions in the receive vectors (DUT failure) is supported by recognizing several types of error indications and an ability to selectively disable the testing of one or more DUTs while continuing to test the one or more that are not disabled. Also included are ways to remove or limit stimulus to particular DUTs, and ways to make all comparisons for a particular DUT appear to be “good. ”.

6570397, May 27, 2003

Aug 7, 2001

09/923548

Romi Mayder - San Jose CA
Noriyuki Sugihara - Campbell CA
Andrew Tse - Castro Valley CA
Randy L. Bailey - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

G01R 3102

324754, 3241581

Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time. In some embodiments, test channels are connected directly to calibration board comparators to avoid the accumulated signal degradation and the signal path route errors that may result from transmitting tester channel signals through a mechanical relay selection matrix.

6373312, Apr 16, 2002

Sep 29, 2000

09/672030

Robert K. Barnes - Ft. Collins CO
Randy L. Bailey - Fort Collins CO

Agilent Technologies, Inc. - Palo Alto CA

H03H 1126

327261, 327276

A precision delay system allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry. The system allows the use of delay elements with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.

5995121, Nov 30, 1999

Oct 16, 1997

8/951356

Byron A. Alcorn - Fort Collins CO
Howard D. Stroyan - Fort Collins CO
Randy L. Bailey - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1516, G06F 1314

345520

An improved method of incorporating a high performance graphics device into a base graphics subsystem of a processor includes two pairs of interface chips. One pair of interface chips is used to transfer pixel data between a base graphics system and the high performance graphics device, while the second pair of interface chips is used to transfer commands between the graphics device and the base graphics system. One of the pair of interface chips that is used to transfer pixel data is coupled to a bus within the base graphics subsystem while the second one of the pair is coupled to the graphics device. With such an arrangement, a high speed interface allows for pixel data to be fed directly to the frame buffer of the graphics subsystem, enabling the windows that are rendered by two different graphics systems to share a frame buffer memory.

7106081, Sep 12, 2006

Jul 8, 2004

10/886848

Romi Mayder - San Jose CA, US
Todd Sholl - San Jose CA, US
Nasser Ali Jafari - Falls Church VA, US
Andrew Tse - Castro Valley CA, US
Randy L. Bailey - Fort Collins CO, US

Verigy IPco - Singapore

G01R 31/02

324758

A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.