PETER LAI, PHARM.D.
Pharmacy at Holger Way, San Jose, CA

6775813, Aug 10, 2004

Sep 10, 2002

10/238357

Sachin Chopra - Cupertino CA
Yu-Yen Mo - San Jose CA
Shyam Sundar - Sunnyvale CA
Peter F. Lai - San Jose CA
Venkat Podduturi - San Jose CA
Vishal Chopra - Cupertino CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 945

716 10, 716 8, 716 9

The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.

6779131, Aug 17, 2004

May 1, 2001

09/846943

Rambabu Pyapali - Santa Clara CA
Xuejun Yuan - Sunnyvale CA
Xiaowei Jin - Mountain View CA
Peter Lai - San Jose CA
Samer H. Haddad - Fremont CA
Jeffrey Wong - Fremont CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1100

714 8

The present invention relates to a method and apparatus for a reconfigurable multi-chip module. The reconfigurable multi-chip module includes a processor; a memory module connected to the processor; and a memory control component for controlling whether the processor uses the memory module. The method of producing multi-chip modules includes assembling a processor and a memory module on the multi-chip module; testing the memory module; and selectively configuring the processor to use the memory module based on the testing of the memory module.

7036096, Apr 25, 2006

Sep 8, 2003

10/657431

Aveek Sarkar - Mountain View CA, US
Yongning Sheng - Sunnyvale CA, US
Peter F. Lai - San Jose CA, US
Rambabu Pyapali - Cupertino CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 17/50

716 1, 716 5, 716 11, 716 18

The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool () to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element () aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (), which uses the total capacitance of each input or output to generate a timing model for the circuit.

2004004, Mar 11, 2004

Sep 6, 2002

10/236840

Mohammed Rahman - Santa Clara CA, US
Langya Yang - Sunnyvale CA, US
Yongjun Zhang - Sunnyvale CA, US
Victor Leung - Sunnyvale CA, US
Hui Lu - Sunnyvale CA, US
Shunjiang Xu - Sunnyvale CA, US
Rambabu Pyapali - Cupertino CA, US
Peter Lai - San Jose CA, US
Chin-Chang Wu - Saratoga CA, US

Sun Microsystems, Inc.

G06F017/50

716/004000

The present invention describes a method and an apparatus for waiving noise violations during semiconductor integrated circuit design. The noise violations in a circuit area (e.g., an individual cell, block of cells or the like) are identified using a threshold look-up table. The threshold look-up table includes different thresholds for each circuit area. The threshold look-up table is generated using various cell related information including practical noise handling limits of each cell that can be higher than traditional noise limits. The information in the threshold look-up table helps eliminate benign noise violations and a new noise report is generated. The new noise report incorporates the practical noise handling capabilities of the cell under analysis and identifies actual noise violations in the semiconductor integrated circuit.

7032200, Apr 18, 2006

Sep 9, 2003

10/657964

Sriram Satakopan - Sunnyvale CA, US
Arvindvel Shanmugavel - Mountain View CA, US
Shunjiang Xu - Sunnyvale CA, US
Von-Kyoung Kim - Santa Clara CA, US
Peter Lai - San Jose CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 17/50

716 6, 716 4, 716 5

A technique improves the performance of an integrated circuit design by selectively replacing low Vtransistors with standard Vtransistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low Vvariant of a gate instance increases a path cycle time as compared to a standard Vcounterpart, the maximum of the path cycle times for all paths that include the low Vvariant and the maximum of the path cycle time for these paths with a standard Vvariant are calculated. If the maximum path cycle time for the path including the low Vvariant is greater than the maximum path cycle time for the path including the standard Vvariant, then that low Vvariant is substituted with a standard Vvariant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.

7484193, Jan 27, 2009

Aug 28, 2003

10/651113

Aveek Sarkar - Mountain View CA, US
Peter Lai - San Jose CA, US
Rambabu Pyapali - Cupertino CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 17/50

716 6, 716 1

The timing response of a circuit path is predicted by modeling the circuit path using two different timing models. The variation between the timing responses produced by each of the timing models is used to generate a correction factor, which is then applied to one of the timing models. Once the correction factor has been applied to a timing model, the model is used to produce a corrected timing prediction for the modeled circuit path.

7007256, Feb 28, 2006

Mar 6, 2003

10/383092

Aveek Sarkar - Mountain View CA, US
Shyam Sundar - Sunnyvale CA, US
Peter F. Lai - San Jose CA, US
Rambabu Pyapali - Cupertino CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 9/45, G06F 9/455, G06F 17/50

716 6, 716 4, 716 11, 703 14, 703 19

The present invention describes a method and an apparatus for determining switching power consumption of global devices (e. g. , repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.

6954914, Oct 11, 2005

Mar 24, 2003

10/395436

Shyam Sundar - Sunnyvale CA, US
Aveek Sarkar - Mountain View CA, US
Peter F. Lai - San Jose CA, US
Rambabu Pyapali - Cupertino CA, US
Teong Ming Cheah - Sunnyvale CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F017/50

716 5, 716 6, 716 2

The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.

7284215, Oct 16, 2007

Mar 11, 2004

10/798046

Von-Kyoung Kim - Santa Clara CA, US
Dakshesh Amin - Sunnyvale CA, US
Sriram Satakopan - Bangalore, IN
Peter F. Lai - San Jose CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 17/50

716 6, 716 5

A technique for improving multiple critical timing paths that exhibit similar characteristics has been discovered. The technique efficiently improves multiple critical timing paths by reducing the number of unique critical timing path patterns for analysis. In some embodiments of the present invention a method for use in connection with an integrated circuit design includes identifying distinct timing paths of the integrated circuit design. The distinct timing paths have timing violations. The method includes associating a first plurality of the distinct timing paths with a first set of timing paths. Individual ones of the first plurality belonging to a second set of timing paths and include a first common characteristic. The method includes improving the first set of timing paths based at least in part on an improvement to an individual timing path of the first set of timing paths.