DR. PETER H CHANG, DO
Medical Practice at Graham, Portland, OR
License number
Oregon DO26736
Category
Medical Practice
Type
Pediatric Cardiology
License number
Oregon OP00002095
Category
Medical Practice
Type
Pediatric Cardiology
Address
Address
2
501 N Graham St SUITE 220, Portland, OR 97227
PO Box 821350, Vancouver, WA 98682
PO Box 821350, Vancouver, WA 98682
Phone
(503) 280-3418
(360) 687-5221
(360) 666-0466 (Fax)
(360) 687-5221
(360) 666-0466 (Fax)
Personal information
See more information about PETER H CHANG at radaris.comName
Address
Phone
3137 NE 20Th Pl, Renton, WA 98056
5236 Hilton Rd NE, Olympia, WA 98516
9618 Bee Dee Dr NE, Olympia, WA 98516
3028 Chapin Dr, Portland, OR 97229
118 107Th Ave NE, Bellevue, WA 98004
Organization information
See more information about PETER H CHANG at bizstanding.comPediatric Cardiology Ctr-Or - Peter H Chang Do
501 N Graham St STE 220, Portland, OR 97227
Categories:
Cardiology Physicians & Surgeons, Osteopathic Physicians & Surgeons, Pediatrics Physicians & Surgeons, ...
Phone:
(503) 280-3418 (Phone)
Professional information
See more information about PETER H CHANG at trustoria.com
Dr. Peter H Chang, Portland OR - DO (Doctor of Osteopathic Medicine)
Dr. Peter H Chang, Portland OR - DO (Doctor of Osteopathic Medicine)
Specialties:
Pediatric Cardiology
Address:
Pediatric Cardiology Center of OR
501 N Graham St SUITE 220, Portland 97227
(503) 280-3418 (Phone), (503) 284-7885 (Fax)
501 N Graham St SUITE 220, Portland 97227
(503) 280-3418 (Phone), (503) 284-7885 (Fax)
Certifications:
Pediatric Cardiology, 2010, Pediatrics, 2007
Awards:
Healthgrades Honor Roll
Languages:
English, Korean
Hospitals:
Pediatric Cardiology Center of OR
501 N Graham St SUITE 220, Portland 97227
Legacy Emanuel Medical Center
2801 North Gantenbein Ave, Portland 97227
Providence Saint Vincent Medical Center
9205 West Barnes Rd, Portland 97225
501 N Graham St SUITE 220, Portland 97227
Legacy Emanuel Medical Center
2801 North Gantenbein Ave, Portland 97227
Providence Saint Vincent Medical Center
9205 West Barnes Rd, Portland 97225
Education:
Medical School
Nova Southeastern University College Of Osteopathic Medicine
Graduated: 2000
Nova Southeastern University College Of Osteopathic Medicine
Graduated: 2000
Peter H Chang, Portland OR
Peter H Chang, Portland OR
Specialties:
Pediatric Cardiologist
Address:
501 N Graham St, Portland, OR 97227
Education:
Doctor of Osteopathy
Board certifications:
American Board of Pediatrics Certification in Pediatrics, American Board of Pediatrics Sub-certificate in Pediatric Cardiology (Pediatrics)
Self-Aligned Selective Metal Contact To Source/Drain Diffusion Region
Self-Aligned Selective Metal Contact To Source/Drain Diffusion Region
US Patent:
8405132, Mar 26, 2013
Filed:
Oct 22, 2010
Appl. No.:
12/910735
Inventors:
Peter Chang - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/78
US Classification:
257288, 257296, 257774, 257382, 257388, 977938
Abstract:
A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate formed on the diffusion region, and insulating side walls formed adjacent to the sacrificial gate. A metal gate is formed by etching out the sacrificial gate and filling in the space between the insulating side walls with gate metals. Silicided source and drain contacts are formed over the diffusion region between the side walls of two adjacent aluminum gates. One or more oxide layers are formed over the substrate. Vias are formed in the oxide layers by plasma etching to expose the silicided source and drain contacts, which simultaneously oxidizes the aluminum gate metal. A first metal is selectively formed over the silicided contact by electroless deposition, but does not deposit on the oxidized aluminum gate.
Intergration Of A Floating Body Memory On Soi With Logic Transistors On Bulk Substrate
Intergration Of A Floating Body Memory On Soi With Logic Transistors On Bulk Substrate
US Patent:
2010000, Jan 14, 2010
Filed:
Sep 16, 2009
Appl. No.:
12/586133
Inventors:
Peter L.D. Chang - Portland OR, US
International Classification:
H01L 27/12
US Classification:
257347, 257E27112
Abstract:
A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.
Memory With Split Gate Devices And Method Of Fabrication
Memory With Split Gate Devices And Method Of Fabrication
US Patent:
2006012, Jun 15, 2006
Filed:
Feb 8, 2006
Appl. No.:
11/350230
Inventors:
Peter Chang - Portland OR, US
International Classification:
H01L 27/12
US Classification:
257347000
Abstract:
A DRAM fabricated on an SOI substrate employing single body devices as memory cells without relying on a field through the insulative layer of the SOI is described. Floating body devices are defined by orthogonally disposed lines with both a front gate and back gate for each body being formed on the insulative layer.
Integration Of A Floating Body Memory On Soi With Logic Transistors On Bulk Substrate
Integration Of A Floating Body Memory On Soi With Logic Transistors On Bulk Substrate
US Patent:
2008011, May 15, 2008
Filed:
Nov 13, 2006
Appl. No.:
11/598980
Inventors:
Peter L.D. Chang - Portland OR, US
International Classification:
H01L 27/06, H01L 21/77
US Classification:
257350, 438151, 257E21598, 257E27014
Abstract:
A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.
Method And Resultant Structure For Floating Body Memory On Bulk Wafer
Method And Resultant Structure For Floating Body Memory On Bulk Wafer
US Patent:
2008015, Jun 26, 2008
Filed:
Dec 22, 2006
Appl. No.:
11/644500
Inventors:
Peter L.D. Chang - Portland OR, US
International Classification:
H01L 27/12, H01L 21/762
US Classification:
257506, 438413, 257E27112, 257E21545
Abstract:
A method for making floating body memory cells from a bulk substrate. A thin silicon germanium and overlying silicon layers are formed on the bulk substrate. Anchors and a bridge are formed to support the silicon layer when the silicon germanium layer is etched so that it can be replaced with an oxide.
Method For Isolating Semiconductor Device Structures And Structures Thereof
Method For Isolating Semiconductor Device Structures And Structures Thereof
US Patent:
2006007, Apr 6, 2006
Filed:
Sep 30, 2004
Appl. No.:
10/956320
Inventors:
Peter Chang - Portland OR, US
International Classification:
H01L 21/4763
US Classification:
438618000
Abstract:
An array of continuous diffusion regions and continuous gate electrode structures is formed over a semiconductor substrate. Interconnecting diffusion region portions and interconnecting gate electrode portions are removed to electrically isolate transistor circuitry. The removal of interconnecting diffusion region portions and gate electrode portions can be performed sequentially, at substantially the same time, and before or after forming source/drain contacts.
Independently Accessed Double-Gate And Tri-Gate Transistors In Same Process Flow
Independently Accessed Double-Gate And Tri-Gate Transistors In Same Process Flow
US Patent:
2010029, Nov 25, 2010
Filed:
Aug 6, 2010
Appl. No.:
12/852408
Inventors:
Peter L.D. Chang - Portland OR, US
Brian S. Doyle - Portland OR, US
Brian S. Doyle - Portland OR, US
International Classification:
H01L 21/3205, H01L 27/088
US Classification:
438585, 257401, 257E27011, 257E21598
Abstract:
A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.
Expitaxial Fabrication Of Fins For Finfet Devices
Expitaxial Fabrication Of Fins For Finfet Devices
US Patent:
2008015, Jul 3, 2008
Filed:
Dec 29, 2006
Appl. No.:
11/647987
Inventors:
Peter L.D. Chang - Portland OR, US
International Classification:
H01L 29/78, H01L 21/336
US Classification:
257288, 438299, 257E21409, 257E29255
Abstract:
A fin for a finFET is described. The fin is a portion of a layer of material, where, another portion of the layer of material resides on a sidewall.