PETER F GRAY, CASAC
Social Work at Franklin St, Schenectady, NY

4883767, Nov 28, 1989

Jul 14, 1988

7/220353

Peter V. Gray - Scotia NY
Bantval J. Baliga - Schenectady NY
Mike F. S. Chang - Cary NC
George C. Pifer - North Syracuse NY

General Electric Company - Schenectady NY

H01L 21265

437 41

A self aligned method of fabricating a self aligned semiconductor device employs an initial step in which a first window having an inner perimeter and outer perimeter is opened through a first protective layer situated atop a semiconductor substrate, to divide the substrate into three separate zones. The window exposes a first surface portion of the semiconductor substrate and circumferentially defines or encompasses a second central portion of the protective layer as well as a second unexposed surface portion of the substrate. A third surface portion of the substrate lies beyond the outer perimeter of the first window. Precisely aligned substrate regions of the same or different conductivity type can be established by using differentially etchable materials to mask designated surface portions of the substrate.

4567641, Feb 4, 1986

Sep 12, 1984

6/650314

Bantval J. Baliga - Clifton Park NY
Peter V. Gray - Scotia NY
Robert P. Love - Schenectady NY

General Electric Company - Schenectady NY

H01L 21441, H01L 21465

29571

An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N. sup. + SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N. sup. + SOURCE through the same window. The etchant removes most of the N. sup. + SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N. sup. + SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.

4656493, Apr 7, 1987

Feb 5, 1985

6/698498

Michael S. Adler - Schenectady NY
Peter V. Gray - Schenectady NY

General Electric Company - Schenectady NY

H01L 2978

357 234

Power MOSFET devices useful in synchronous rectifier circuit applications are bidirectional and symmetrical for use in AC circuits, and have low on-resistance, fast switching speed, and high voltage capability. In one embodiment, a planar enhancement-mode diffused MOSFET structure obviates the source-to-base short conventionally included to prevent turn-on of the parasitic bipolar transistor defined by the main terminal regions of one conductivity type and the intermediate base region of opposite conductivity type, by employing within the base region a recombination region having a relatively small lifetime for excess base region majority-carriers in order to inhibit operation of the parasitic bipolar transistor. Another embodiment resembles a pair of conventional, vertical-current, MOSFET unit cells formed symmetrically back-to-back and sharing a common drain region which serves only as an intermediate terminal region not directly connected to any device terminal. To inhibit operation of the several parasitic bipolar transistors and thyristor switching device structures inherent in this embodiment, an ohmic short is provided between the source and base regions of each of the unit cells, and a recombination region having a relatively small lifetime for intermediate terminal region majority-carriers is formed within the intermediate terminal region between the spaced base regions of the unit cells.

4262296, Apr 14, 1981

Jul 27, 1979

6/061450

James R. Shealy - Clifton Park NY
Bantval J. Baliga - Clifton Park NY
Wirojana Tantraporn - Schenectady NY
Peter V. Gray - Scotia NY

General Electric Company - Schenectady NY

H01L 2906

357 55

A high frequency field effect transistor of gallium arsenide or other III-V semiconductor compounds has a preferentially etched trapezoidal groove structure in the top surface which creates parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Schottky gates or junction gates are fabricated within the grooves surrounding the elongated fingers. The vertical conducting channels between the gates are narrow leading to a high blocking gain, and more contact area is available at the top of the device.

5041896, Aug 20, 1991

Jul 6, 1989

7/376073

Victor A. K. Temple - Clifton Park NY
Stephen D. Arthur - Scotia NY
Peter V. Gray - Scotia NY

General Electric Company - Schenectady NY

H01L 2740, H01L 27120, H01L 29000

357 50

An improved symmetrical blocking high voltage semiconductor device structure incorporating a sinker region and a buried region adjacent the periphery of the chip improves device operating characteristics and simplifies device fabrication processes. A heavily doped polycrystalline refill of a trench provides a deep junction sidewall region which brings the lower high voltage blocking junction to the upper surface.