MR. PETER CAMPORESE
Pharmacy in East Fishkill, NY

6341365, Jan 22, 2002

Sep 15, 1999

09/396327

Robert P. Dwyer - New Paltz NY
Peter J. Camporese - Hopewell Junction NY

International Business Machines Corporation - Armonk NY

G06F 1750

716 8, 716 2, 716 6, 716 9

A method (and a system for using the method) for placing a semiconductor circuit device between a driver and one or more receivers on the floor space of a chip. The method includes the steps of: determining respective distances between the driver and each of the one or more receivers; determining a shortest of the distances; determining midpoint along the shortest distance; determining whether the midpoint is predesignated to the floor space of one or more blocking semiconductor circuit devices; placing the repeater at the midpoint if the midpoint is not predesignated to the one or more blocking semiconductor circuit devices; and applying a backoff algorithm to incrementally back away from the midpoint to an optimal location, and placing the repeater at the optimal location, if the midpoint is predesignated to the one or more blocking semiconductor circuit devices. The method can also include the steps of: determining whether the to be placed semiconductor circuit device can be placed at a set of incremental locations located along one or more axes away from the midpoint; and placing the to be placed semiconductor circuit device at one of the one or more acceptable incremental locations. The step of determining the set of incremental locations can be performed in a spiral pattern away from the midpoint.

6487706, Nov 26, 2002

Aug 30, 2000

09/651464

Keith G. Barkley - Poughquaq NY
Peter J. Camporese - Hopewell Junction NY
Kwok Fai Eng - Kingston NY

International Business Machines Corporation - Armonk NY

G06F 1750

716 7, 716 13

A method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, begins by defining a size for the chip of a hierarchical design, and then removing blocked areas, including clock and power grid areas leaving the wiring channels available for interconnecting the individual elements of the VLSI chip. A percentage of the available area is allocated for wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress. During the parallel iterative process the number of wires increases for the power grid area to prevent a signal wire from having an active wire on either side of the signal wire. In the interactive process, a vertical slice of wiring resources used for the space above a macro entity is defined and the macro entity is checked with the context of the VLSI chip physical design above it. The process employs a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools.

6546529, Apr 8, 2003

Oct 2, 2000

09/677362

Allan H. Dansky - Poughkeepsie NY
Michael A. Bowen - Poughkeepsie NY
Peter J. Camporese - Hopewell Junction NY
Alina Deutsch - Chappaqua NY
Howard H. Smith - Beacon NY

International Business Machines Corporation - Armonk NY

G06F 945

716 5, 716 4, 716 6

Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available. The steps include: creating a flat wire routing map of the integrated circuit, identifying the coupled wire segments on the integrated circuit, tracking wire interconnection patterns on the integrated circuit, deriving electrical parameters for the coupled wire segments, and generating a coupling guideline table with parameters for a plurality of electrical parameters. The parameters in the coupling guideline table are applied to the derived electrical parameters and a report is generated that lists the derived electrical parameters that fail to comply with the parameters in the coupling guideline table.

6618843, Sep 9, 2003

Jun 29, 2001

09/896269

Allan H. Dansky - Poughkeepsie NY
Wiren D. Becker - Hyde Park NY
Howard H. Smith - Beacon NY
Peter J. Camporese - Hopewell Junction NY
Kwok Fai Eng - Kingston NY
Dale E. Hoffman - Fishkill NY
Bhupindra Singh - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

G06F 1750

716 5, 716 10

A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

6618844, Sep 9, 2003

Jun 29, 2001

09/896270

Allan H. Dansky - Poughkeepsie NY
Wiren D. Becker - Hyde Park NY
Howard H. Smith - Beacon NY
Peter J. Camporese - Hopewell Junction NY
Kwok Fai Eng - Kingston NY
Dale E. Hoffman - Fishkill NY
Bhupindra Singh - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

G06F 1750

716 5, 716 10

A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

6460169, Oct 1, 2002

Oct 21, 1999

09/422040

Peter J. Camporese - Hopewell Junction NY
Allan H. Dansky - Poughkeepsie NY
Howard H. Smith - Beacon NY

International Business Machines Corporation - Armonk NY

G06F 1750

716 10, 716 13

A routing program length method for positioning unit pins in a hierarchically designed VLSI chip first identifies unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a “flat” file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the Incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins.

6311313, Oct 30, 2001

Dec 29, 1998

9/222141

Peter J. Camporese - Hopewell Junction NY
Alina Deutsch - Chappaqua NY
Timothy Gerard McNamara - Fishkill NY
Phillip John Restle - Katonah NY
David Allan Webber - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

G06F 945

716 6

An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.

6205571, Mar 20, 2001

Dec 29, 1998

9/222143

Peter J. Camporese - Hopewell Junction NY
Alina Deutsch - Chappagua NY
Timothy Gerard McNamara - Fishkill NY
Phillip John Restle - Katonah NY
David Allan Webber - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

G06F 1750

716 2

An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid.

5455931, Oct 3, 1995

Nov 19, 1993

8/155178

Peter J. Camporese - Hopewell Junction NY
Patrick J. Meaney - Poughkeepsie NY
Brian J. O'Leary - Hyde Park NY
Richard F. Rizzolo - Red Hook NY

International Business Machines Corporation - Armonk NY

G06F 104

395550

A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.

6323050, Nov 27, 2001

Oct 2, 2000

9/677285

Allan H. Dansky - Poughkeepsie NY
Wiren D. Becker - Hyde Park NY
Howard H. Smith - Beacon NY
Peter J. Camporese - Hopewell Junction NY
Kwok Fai Eng - Kingston NY
Dale E. Hoffman - Fishkill NY
Bhupindra Singh - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 2166

438 17

A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.