PAUL Y. WONG, MD
Anesthesiologist Assistant at International Cir, San Jose, CA

6658617, Dec 2, 2003

May 11, 2000

09/570158

Paul Wong - San Jose CA

Fujitsu Limited - Kawasaki

G01R 3128

714733, 714734, 326 46

An apparatus for obtaining valid values during a built-in self-testing of logic (“LBIST”) is disclosed. The apparatus includes a first multiplexer, a second multiplexer and a 1-hot init circuit. The 1-hot init circuit includes a scan register, a first inverter, a third multiplexer, a second inverter, and a fourth multiplexer. The scan register includes a plurality of state elements. The first multiplexer is coupled to receive a random data signal and an output of the 1-hot init circuit. Within the 1-hot init circuit, a next to last and a last state element of the scan register is coupled to the inverters and the third and fourth multiplexers, respectively. The first inverter is also coupled to the third multiplexer and the second inverter is coupled to the fourth multiplexer. The output of the fourth multiplexer is coupled to the input of the second multiplexer. Also coupled to the input of the second multiplexer is an input for the random data signal.

6636997, Oct 21, 2003

Oct 24, 2000

09/695749

Paul Wong - San Jose CA
Mark O. Porter - Los Gatos CA
Dwight K. Elvey - Santa Cruz CA

Fujitsu Limited - Kawasaki

G01R 3128

714728, 714729

The initialization process and structure of the system ensure that during loading of random data a 1-hot condition is maintained to the 1-hot multiplexer so as to prevent contention or a high current state. The present invention further improves observability of intermediate stages by preventing random data feeding of the state elements in scan chains that cannot tolerate random data. A scan chain having only scan registers that can receive random data is referred to as a LBIST Random Scan Chain (LRSC) and a scan chain having one or more scan registers that cannot tolerate and cannot receive random data is referred to as a “LBIST Non-random Scan Chain” (LNSC). A PRPG generates random data having a plurality of bit values to the LRSCs which is then passed to a multiple input shift register (MISR). The LNSCs do not receive random data from the PRPG but instead receive bit values from another scan chain. Before feeding bit values into a LNSC, the bit values are feed into a decoder and the LNSCs feed bit values reflecting test responses into the MISR.

7643979, Jan 5, 2010

Jan 17, 2006

11/334063

Qiang Hong - San Jose CA, US
Kevin D. Jones - Hayward, GB
Paul Wong - San Jose CA, US

Rambus Inc. - Los Altos CA

G06F 17/50, G01R 31/28

703 14, 703 22, 716 5, 702 85, 702109

Data structures and algorithms are provided to automatically generate an analog stimulus to apply to a simulation of the analog DUT. A constraint solver is provided to determine suitable values to use in the stimulus generation. The suitable values are random values within a range of allowed values. For example, a number of different stimuli are generated for successive application to the analog DUT, each with a different magnitude within a range of allowed magnitudes. Data structures and algorithms are provided to monitor analog electrical properties at nodes of the analog DUT. Data structures and algorithms are provided to define constraints on the analog electrical properties and determine whether the constraints were violated. Data structures and algorithms are provided to define simulation coverage conditions in the analog domain and determine whether the defined analog domain coverage conditions have been satisfied.

7392492, Jun 24, 2008

Sep 30, 2005

11/242598

Qiang Hong - San Jose CA, US
Jing Jiang - Stanford CA, US
Kevin D. Jones - Hayward CA, US
Kathryn M. Mossawir - Stanford CA, US
Thomas J. Sheffler - San Francisco CA, US
Paul Wong - San Jose CA, US

Rambus Inc. - Los Altos CA

G06F 17/50

716 5, 716 11

A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.

2008026, Oct 23, 2008

Jun 23, 2008

12/144457

Qiang Hong - San Jose CA, US
JIng Jiang - Stanford CA, US
Kevin D. Jones - Hayward CA, US
Kathryn M. Mossawir - Stanford CA, US
Thomas J. Sheffler - San Francisco CA, US
Paul Wong - San Jose CA, US

G06F 17/50

716 5

A method and system for performing consistency checking of one or more design representations having different design types. A translator for each design type obtains information from each design needed to evaluate rules that are design type-neutral. The described examples also allow a user to add rules using predefined rule terms. In addition, certain examples allow the user to add terms to the rule set and to make new rules with the added terms. Each new term added to a rule set has a corresponding abstraction function in a translator for each design type. Thus, the abstraction functions are not design type-neutral.