PAUL WILLIAM RUDRUD
Pilots at Fireside Ln, Rochester, MN
License number
Minnesota A2898665
Issued Date
Sep 2016
Expiration Date
Sep 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
614 Fireside Ln SW, Rochester, MN 55902
Professional information
Setting Memory Controller Driver To Memory Device Termination Value In A Communication Bus
US Patent:
7990768, Aug 2, 2011
Filed:
Jan 29, 2009
Appl. No.:
12/361577
Inventors:
Benjamin A Fox - Rochester MN, US
William P Hovis - Rochester MN, US
Thomas W Liang - Rochester MN, US
Paul Rudrud - Rochester MN, US
William P Hovis - Rochester MN, US
Thomas W Liang - Rochester MN, US
Paul Rudrud - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 16/04
US Classification:
36518509, 36518909, 365198, 36523006
Abstract:
A method and system are provided for coupling a DRAM and a memory controller during driver training to reduce mismatches by controlling impedances within the system environment. A memory device initializes a bit level voltage on a data net. A driver impedance in a driving element in the controller is modified to yield improvements in timing margins.
Setting Controller Vref In A Memory Controller And Memory Device Interface In A Communication Bus
US Patent:
8102724, Jan 24, 2012
Filed:
Jan 29, 2009
Appl. No.:
12/361719
Inventors:
Benjamin A Fox - Rochester MN, US
William P Hovis - Rochester MN, US
Thomas W Liang - Rochester MN, US
Paul Rudrud - Rochester MN, US
William P Hovis - Rochester MN, US
Thomas W Liang - Rochester MN, US
Paul Rudrud - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
365198, 36518909
Abstract:
A memory device is connected through an interface to a memory controller. The controller's reference voltage is set based on a driver's impendence of the memory device during driver training. The voltage is applied to a reference resistor pair at the controller and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the controller.
Setting A Reference Voltage In A Memory Controller Trained To A Memory Device
US Patent:
8289784, Oct 16, 2012
Filed:
Jun 15, 2010
Appl. No.:
12/815739
Inventors:
Benjamin A. Fox - Rochester MN, US
William P. Hovis - Rochester MN, US
Thomas W. Liang - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
William P. Hovis - Rochester MN, US
Thomas W. Liang - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
36518909, 36518911, 36523313, 326 30, 326 83, 326 86
Abstract:
Systems and methods to set a voltage value associated with a memory controller coupled to a memory device are disclosed. A particular method includes comparing test data of a test path to functional data of a functional path. The functional data may be generated based on device data received at a memory controller from a memory device. The test data may be affected by a voltage value applied to a resistor arrangement in electronic communication with the test path. The voltage value may be applied to the resistor arrangement based on the comparison.
Setting Controller Termination In A Memory Controller And Memory Device Interface In A Communication Bus
US Patent:
8111564, Feb 7, 2012
Filed:
Jan 29, 2009
Appl. No.:
12/361836
Inventors:
Benjamin A Fox - Rochester MN, US
William P Hovis - Rochester MN, US
Thomas W Liang - Rochester MN, US
Paul Rudrud - Rochester MN, US
William P Hovis - Rochester MN, US
Thomas W Liang - Rochester MN, US
Paul Rudrud - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 7/00
US Classification:
36518918, 36518917, 36523313, 365149
Abstract:
A DRAM and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the controller to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.
Training A Memory Controller And A Memory Device Using Multiple Read And Write Operations
US Patent:
2011030, Dec 15, 2011
Filed:
Jun 15, 2010
Appl. No.:
12/815844
Inventors:
Benjamin A. Fox - Rochester MN, US
William P. Hovis - Rochester MN, US
Thomas W. Liang - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
William P. Hovis - Rochester MN, US
Thomas W. Liang - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00, H03K 19/003
US Classification:
711154, 326 30
Abstract:
Systems and methods to set a voltage value associated with a communication bus that includes memory controller coupled to a memory device are disclosed. A particular method may include performing a first calibration operation associated with first data written from a memory controller to a memory device. A second calibration operation may be associated with second data read at the memory controller from the memory device. The operating parameter may be set based on a result of at least one of the first and the second calibration operations at the memory device or the memory controller.
Method Of Enabling Triggering An Oscilloscope
US Patent:
2009026, Oct 29, 2009
Filed:
Apr 29, 2008
Appl. No.:
12/111353
Inventors:
Emmanuel Atta - Rochester MN, US
Paul Rudrud - Rochester MN, US
Paul Rudrud - Rochester MN, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G01R 1/067
US Classification:
324149
Abstract:
A method of enabling triggering an oscilloscope includes placing a tip portion of a probe, electrically connected to the oscilloscope, on an electrical circuit, applying pressure to the probe tip, and establishing an electrical contact inside the probe as a result of pressure applied to the probe tip. The electrical contact closes an electrical circuit that triggers the oscilloscope.
Memory Device Verification Of Multiple Write Operations
US Patent:
7603528, Oct 13, 2009
Filed:
Oct 8, 2004
Appl. No.:
10/961745
Inventors:
William Hugh Cochran - Rochester MN, US
William Paul Hovis - Rochester MN, US
Paul Rudrud - Rochester MN, US
William Paul Hovis - Rochester MN, US
Paul Rudrud - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/28, G06F 11/00
US Classification:
711162, 711159, 714737
Abstract:
Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.
High Density Printed Circuit Board Interconnect And Method Of Assembly
US Patent:
2009027, Nov 12, 2009
Filed:
May 10, 2008
Appl. No.:
12/118696
Inventors:
John R. Dangler - Rochester MN, US
Matthew S. Doyle - Rochester MN, US
Jesse M. Hefner - Rochester MN, US
Thomas W. Liang - Rochester MN, US
Ankur K. Patel - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
Matthew S. Doyle - Rochester MN, US
Jesse M. Hefner - Rochester MN, US
Thomas W. Liang - Rochester MN, US
Ankur K. Patel - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
International Classification:
H05K 1/02
US Classification:
174255
Abstract:
A printed circuit board assembly having an edge joined first and second sub-circuit board is provided. The first sub-circuit board includes an edge with a stair-step profile interconnection wherein each of the stairs on the profile exposes an area of a signal layer. Each exposed portion of the signal layer has a plurality of signal pads thereon. The second sub-circuit board includes an edge with an inverse stair-step profile interconnection. A pad-on-pad connector is positioned in-between and electrically interconnects the respective signal layers on each sub-circuit board.
Efficient Memory Usage In Systems Including Volatile And High-Density Memories
US Patent:
7613870, Nov 3, 2009
Filed:
Nov 18, 2004
Appl. No.:
10/992443
Inventors:
Gerald K. Bartley - Rochester MN, US
John M. Borkenhagen - Rochester MN, US
William H. Cochran - Rochester MN, US
William P. Hovis - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
John M. Borkenhagen - Rochester MN, US
William H. Cochran - Rochester MN, US
William P. Hovis - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711103, 711118, 711154
Abstract:
A first method for efficient memory usage includes (1) determining whether data retrieved from a first storage device is characterized as data that is primarily read; and (2) if data retrieved from the first storage device is characterized as data that is primarily read (a) writing the retrieved data in a temporary storage device with short write latency; and (b) writing the retrieved data in a high-density memory. Numerous other aspects are provided.
Implementing Memory Read Data Eye Stretcher
US Patent:
7661084, Feb 9, 2010
Filed:
Oct 18, 2007
Appl. No.:
11/874366
Inventors:
William Paul Hovis - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
Paul W. Rudrud - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 10, 716 8, 716 9, 716 11, 375317, 711167, 711211, 36518909
Abstract:
A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher and a design structure on which the subject circuit resides is provided. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the reference level for the current data being latched so that the data eye is maximized.