PAUL H DAVIS
Real Estate Commission in Reading, PA

License number
Pennsylvania RS178065L
Category
Real Estate Commission
Type
Real Estate Salesperson-Standard
Address
Address
Reading, PA 19606

Personal information

See more information about PAUL H DAVIS at radaris.com
Name
Address
Phone
Paul Davis, age 66
5115 Chevy Chase Dr, Finleyville, PA 15332
(724) 348-5591
Paul Davis, age 94
502 Bow Ln, Gilbertsville, PA 19525
(610) 952-9016
Paul Davis, age 79
502 Pawnee Dr, Mechanicsburg, PA 17050
(717) 972-8490
Paul Davis, age 63
521 Cedarhurst St, Pittsburgh, PA 15210
(412) 427-7262
Paul Davis, age 63
521 Northfield Rd, Devon, PA 19333
(610) 687-2749

Professional information

See more information about PAUL H DAVIS at trustoria.com
Paul Davis Photo 1
Retired At Lucent Bell Labs

Retired At Lucent Bell Labs

Position:
Retired at Lucent Bell Labs
Location:
Reading, Pennsylvania Area
Industry:
Nonprofit Organization Management
Work:
Lucent Bell Labs since Mar 2001 - Retired IEEE-BCTM Apr 2007 - Dec 2009 - Treasurer (Volunteer) ISSCC 1993 - 2003 - Technical Program Committee Member AT&T Bell Labs Oct 1962 - Mar 2001 - DMTS Lucent/Agere 1962 - 2001 - DMTS AT&T Bell Laboratories 1962 - 2001 - DMTS Bell Labs/Lucent 1962 - 2001 - MTS/DMTS Lucent Technologies 1962 - 2001 - DMTS Bell Labs 1962 - 2001 - MTS/DMTS Bell Laboratories 1962 - 2001 - DMTS
Education:
WVU, MIT, Lehigh 1954 - 1968
BS, MS, PhD, EE


Paul Davis Photo 2
Balancing Circuit, Method Of Operation Thereof And A Charge Pump Employing The Same

Balancing Circuit, Method Of Operation Thereof And A Charge Pump Employing The Same

US Patent:
6798298, Sep 28, 2004
Filed:
Nov 16, 2001
Appl. No.:
09/993588
Inventors:
Paul C. Davis - Reading PA
Irving G. Post - Reading PA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03L 700
US Classification:
331 16, 331 25, 327264, 327285, 327413
Abstract:
A balancing circuit and method of operation thereof for use with a circuit having first and second complementary drivers exhibiting different current gain characteristics. In one embodiment, the balancing circuit includes a sensing subcircuit that provides a correction signal indicating a first current gain characteristic of the first driver. The balancing circuit also includes a compensation subcircuit that generates a current gain compensation signal to the first driver to substantially match a second current gain characteristic of the second driver based on the correction signal.


Paul Davis Photo 3
Bias Circuit For Transconductance Amplifier

Bias Circuit For Transconductance Amplifier

US Patent:
6023196, Feb 8, 2000
Filed:
Aug 3, 1998
Appl. No.:
9/127752
Inventors:
Kirk B. Ashby - Reading PA
Paul C. Davis - Reading PA
Michael D. Womac - Blandon PA
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H03F 130, H03F 345
US Classification:
330290
Abstract:
In low-voltage circuits, there is often insufficient voltage to use a current source to bias a transconductance amplifier stage. This is particularly true in mixers where a switching circuit must be stacked on top of the transconductance input stage. One way around this problem is to get "double-duty" out of the input differential pair, using it both for gain stage and for DC bias. This is done by AC coupling in a high-frequency input signal, while using a low-frequency, DC-coupled circuit to establish the proper bias level. One common technique is to use a simple current mirror scheme to establish the DC level. Proper biasing using this technique requires good matching of resistance. In some implementations of transconductance amplifiers, particularly those that use inductors as degeneration elements, series resistance of the inductor and interconnect resistance can cause significant errors in the bias current. This invention addresses that problem by using an operational amplifier with a current-sensing resistor and a low-frequency feedback loop to compensate automatically for any resistance errors.


Paul Davis Photo 4
Broadband Linear Transconductance Amplifier With Resistive Pole-Splitting Compensation

Broadband Linear Transconductance Amplifier With Resistive Pole-Splitting Compensation

US Patent:
5917379, Jun 29, 1999
Filed:
Jul 31, 1997
Appl. No.:
8/903012
Inventors:
Kirk B Ashby - Reading PA
Paul C. Davis - Reading PA
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H03F 345
US Classification:
330260
Abstract:
A compensation scheme for differential- or single-input transconductance amplifiers relies on an active feedback path with a resistive pole-splitting compensation circuit. The resistive compensation circuit causes pole-splitting of the two dominant poles, moving one pole to a slightly lower frequency and the other to a much higher frequency compared to the dominant poles of the uncompensated amplifier. A DC-blocking capacitor may also be placed in series with the resistor of the compensation circuit to allow for proper biasing of the circuit. By selecting appropriate values for the passive elements in the compensation circuit, the compensation scheme of the present invention can cause the amplifier to operate in a stable, linear manner over the same or even a larger bandwidth than an equivalent amplifier without compensation. The present invention does not suffer the problems of standard narrowbanding compensation schemes associated with high frequency cut-off.


Paul Davis Photo 5
Mixed Signal Integrated Circuit With Improved Isolation

Mixed Signal Integrated Circuit With Improved Isolation

US Patent:
6909150, Jun 21, 2005
Filed:
Jul 23, 2001
Appl. No.:
09/911035
Inventors:
Paul C. Davis - Reading PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L029/76
US Classification:
257368, 257370, 257506, 257508, 257544, 257547, 257372
Abstract:
An integrated circuit having improved isolation includes a first circuit section formed in a substrate and a second circuit section formed in the substrate, the second circuit section being spaced laterally from the first circuit section. The integrated circuit further includes an isolation buried layer formed under at least a portion of the first circuit section, and a conductive layer formed on a surface of the substrate and electrically coupled to the buried layer and to a voltage reference, the conductive layer reducing an effective lateral resistance of the buried layer, whereby an isolation between the first and second circuit sections is increased. A second isolation buried layer can be formed under at least a portion of the second circuit section as well to provide further isolation between the first and second circuit sections.


Paul Davis Photo 6
Low-Voltage Radio Frequency Amplifier

Low-Voltage Radio Frequency Amplifier

US Patent:
5929708, Jul 27, 1999
Filed:
Nov 20, 1997
Appl. No.:
8/974818
Inventors:
Paul Cooper Davis - Muhlenberg Township PA
Milton Luther Embree - Muhlenberg Township PA
Brian K. Horton - Sinking Springs PA
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H03F 304
US Classification:
330288
Abstract:
A power-conserving, linear and broad band RF amplifier, suitable for use at more than one band in the ultra-high frequency regions allotted to radiotelephone transceivers, employs an emitter-follower output transistor to deliver the nominal 1. 0 milliwatt RF power to a single-ended load from a low voltage battery, typically 2. 7 v. dc, without the use of output coupling transformers. The amplifier receives only a small differential input signal from the preceding mixer or multiplier stage having a typical peak-to-peak magnitude of 0. 3 v. The differential input signal is applied to the emitters of a pair of transistors whose bases are interconnected, one transistor of which (B6) is diode-connected in a current-mirror configuration and the other (B5) of which is configured in a common-base connection with emitter degeneration. The signals are summed at the collector of the common-base transistor to deliver a substantial voltage swing, illustratively 1. 7 volts peak to peak, which is large enough to drive the base of the emitter-follower output transistor (B3) without requiring the high standby current in the emitter-follower normally required to maintain an emitterfollower in Class A operation.


Paul Davis Photo 7
Clock Recovery And Retiming Scheme With Saw Filter Phase Trimming To Achieve Desired System Phase Adjustment

Clock Recovery And Retiming Scheme With Saw Filter Phase Trimming To Achieve Desired System Phase Adjustment

US Patent:
4715049, Dec 22, 1987
Filed:
Mar 12, 1986
Appl. No.:
6/838709
Inventors:
George E. Andrews - Fleetwood PA
Paul C. Davis - Reading PA
Dennis C. Farley - Coopersburg PA
Stanley H. Kravitz - Coopersburg PA
Thrygve R. Meeker - Allentown PA
Owe G. Petersen - Reading PA
Arthur W. Schelling - Emmaus PA
Assignee:
American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ
International Classification:
H04L 700
US Classification:
375106
Abstract:
A clock recovery and data retiming circuit is disclosed which utilizes a SAW filter to form the recovered clock signal. The phase shift of the received data signal associated with various attenuation and distortion effects of the communication channel is compensated for and removed from the retimed data signal by adjusting the phase of the SAW filter.


Paul Davis Photo 8
Differential Amplifier With Digitally Controlled Gain

Differential Amplifier With Digitally Controlled Gain

US Patent:
H9652, Sep 3, 1991
Filed:
Jan 26, 1990
Appl. No.:
7/471185
Inventors:
Paul C. Davis - Reading PA
Scott L. Forgues - Wyomissing PA
Iconomos A. Koullias - West Lawn PA
Assignee:
American Telephone and Telegraph Company - New York NY
International Classification:
H03F 345
US Classification:
330254
Abstract:
Differential amplifier having multiple stages, each stage having the gain thereof set by digital control. The gain of each stage is individually controlled, thereby allowing wide dynamic range and gain. Each stage has a differential pair with multiple sets of gain-setting resistors in the emitters of the pair. By selecting which resistor set, or combination of resistor sets, is used, the gain of the stage is controlled. The result is a 4 stage, 0-45 dB gain amplifier for RF or IF applications, with the gain adjustable in 3 dB increments.


Paul Davis Photo 9
Radio Receiver With Dc Offset Correction Circuit

Radio Receiver With Dc Offset Correction Circuit

US Patent:
5724653, Mar 3, 1998
Filed:
Dec 20, 1994
Appl. No.:
8/359782
Inventors:
Thomas Wesley Baker - Orefield PA
Paul Cooper Davis - Reading PA
Douglas D. Lopata - Boyertown PA
Owe George Petersen - Brookfield WI
Trudy Dawn Stetzler - Reading PA
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H04B 112
US Classification:
455296
Abstract:
The present invention relates to a radio receiver adapted for use in a time division multiple access (TDMA) system. The radio receiver includes DC compensator circuits configured to decrease the time required to cancel DC offset before received data bursts by DC coupling a radio frequency (RF) demodulator to a baseband channel. The radio receiver may also employ AC capacitive coupling having time modification so as to increase the AC coupled setting time and provide a low pole in a RF-to-Baseband interface.


Paul Davis Photo 10
Active Speech Network Circuit For A Telephone Set

Active Speech Network Circuit For A Telephone Set

US Patent:
4332984, Jun 1, 1982
Filed:
Dec 13, 1979
Appl. No.:
6/103404
Inventors:
Paul C. Davis - Reading PA
Raymond G. Jackson - Indianapolis IN
Kenneth F. Sodomsky - Reading PA
Dennis L. Whitson - Blue River Township, Hancock County IN
Assignee:
Bell Telephone Laboratories, Incorporated - Murray Hill NJ
International Classification:
H04M 100
US Classification:
179 81R
Abstract:
In a subscriber telephone set, an active speech network provides a sidetone signal and for equalization of the transmit and receive signals at the tip and ring line port and also maintains the dc voltage at a substantially constant level at this port. The network is compatible with conventional telephone sets and operation on long loops in parallel with such sets is provided for. Internal circuitry (320) within the network check both loop current and tip-to-ring voltage to ensure that both are of a magnitude sufficient for a tone signaling dial (301) to properly generate tone signals before enabling the dial.