PAUL G SCOTT
Engineers in Tempe, AZ

License number
Pennsylvania PE049558E
Category
Engineers
Type
Professional Engineer
Address
Address 2
Tempe, AZ 85281
Pennsylvania

Personal information

See more information about PAUL G SCOTT at radaris.com
Name
Address
Phone
Paul Scott
5120 E Hampton Ave APT 1255, Mesa, AZ 85206
(480) 854-1625
Paul Scott
50 E Market St, Hallam, PA 17406
Paul Scott
485 Memorial Hwy, Fleetwood, PA 19522
Paul Scott, age 78
4505 W Taro Dr, Glendale, AZ 85308
(623) 340-4087
Paul Scott, age 95
4837 Race Track Rd, Saint Thomas, PA 17252
(717) 369-3769

Professional information

Paul Scott Photo 1

Buffering For An I.sup.2 L Memory Cell

US Patent:
4099263, Jul 4, 1978
Filed:
Nov 4, 1976
Appl. No.:
5/738779
Inventors:
Paul Howard Scott - Tempe AZ
Assignee:
Motorola Inc. - Schaumburg IL
International Classification:
G11C 1140
US Classification:
365155
Abstract:
A memory cell having input and output buffering. Input buffering is provided by connecting the injector input of an integrated injection logic (I. sup. 2 L) gate to the data input line of the memory cell and by connecting the injector input of the input gates of the memory cell to the write enable line. In order to enter data into the memory cell, the input gates must be energized via the injector input. Output buffering is provided by placing another integrated injection logic gate between the memory cell output and the data output line. The injector input of the another gate is connected to a read select line thereby permitting information contained within the memory cell to be read out to the data output line whenever the read select line connected to the injector input is enabled.


Paul Scott Photo 2

I.sup.2 L Injector Current Source

US Patent:
4075508, Feb 21, 1978
Filed:
Nov 4, 1976
Appl. No.:
5/738778
Inventors:
Paul Howard Scott - Tempe AZ
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 1908, H03K 1940
US Classification:
307213
Abstract:
A switchable injector current source for integrated injection logic (I. sup. 2 L) circuits is provided. An I. sup. 2 L gate having an NPN output transistor with at least two collectors is used to drive an emitter follower. A resistor is connected from the emitter of the emitter follower to one of the collectors of the NPN transistor. The base of the emitter follower is connected to the other collector of the NPN transistor and is also connected to a current source. The output of the switchable injector current source is taken from the junction formed by the collector of the NPN transistor and the resistor.