MR. PAUL CHINGKANG LIN, LIC AC
Acupuncture at Manchaca Rd, Austin, TX

5247423, Sep 21, 1993

May 26, 1992

7/887963

Paul T. Lin - Austin TX
Michael B. McShane - Austin TX

Motorola, Inc. - Schaumburg IL

H05K 720

361719

A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.

5200362, Apr 6, 1993

Sep 9, 1991

7/756952

Paul T. Lin - Austin TX
Michael B. McShane - Austin TX
Sugio Uchida - Nagano, JP
Takehi Sato - Nagano, JP

Motorola, Inc. - Schaumburg IL

H01L 2156, H01L 2158, H01L 2160

437207

A semiconductor device and a method for its fabrication are disclosed. In a preferred embodiment, a pattern of conductive traces is formed on a film of transfer material. A semiconductor device die is interconnected to the pattern of conductive traces and a resin body is formed around the die, one side of the conductive traces, and the interconnecting means. The film of transfer material forms, at this stage of the process, one side of the package. The film of transfer material is then peeled from the pattern of conductive traces and the resin body to expose the other side of the pattern of conductive traces. Contact to the other side of the pattern provides electrical contact to the senmiconductor device die.

5049526, Sep 17, 1991

Jun 7, 1989

7/362644

Michael B. McShane - Austin TX
Paul T. Lin - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 232

437211

A method for fabricating and especially for encapsulating a semiconductor device in a plastic package is disclosed. In accordance with one embodiment of the invention the method includes steps of providing an encapsulation mold having a first chamber and a second chamber, with the second chamber spaced outwardly from and substantially surrounding the first chamber. The first chamber is shaped to receive a removable insert. An insert is selected for the particular body type and style which is desired and that insert is secured in the first chamber. The insert has a cavity which is shaped to define the desired encapsulated device package body. A lead frame is provided including a bonding area and a plurality of leads, each lead having a inner portion near the bonding area and an outer portion extending outwardly from the bonding area. A semiconductor device die is secured to the lead frame and the lead frame with the die attached is aligned within the encapsulation mold to place the semiconductor device die and the inner ends of the leads within the cavity defined by the inserts. The outer ends of the leads extend through the second chamber.

5045914, Sep 3, 1991

Mar 1, 1991

7/663225

James J. Casto - Austin TX
Michael B. McShane - Austin TX
Paul T. Lin - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2348

357 70

A pad array electronic device for mounting on a substrate, such as a printed circuit board (PCB), has a relatively rigid package body with a plurality of holes bearing connecting mechanisms for bonding to lands on the PCB. The package body may be a thermoset plastic or other material that can be injection molded around an electronic component, such as an integrated circuit (IC) bonded to a lead frame. An integrated circuit die or other electronic component is mounted in proximity with or on the lead frame and electrical connections between the integrated circuit chip and the frame are made by any conventional means. In one aspect, the substrate leads are provided at their outer ends that are exposed by holes in the package with solder balls or pads for making connections to the PCB. The package body may be optionally used to stand off the device a set distance from the PCB so that the solder balls will form the proper concave structure. The periphery of the package body may function as a carrier structure to protect the lead or connection structures during testing, handling and board mounting.

5018005, May 21, 1991

Dec 27, 1989

7/457648

Paul T. Lin - Austin TX
Michael B. McShane - Austin TX

Motorola Inc. - Schaumburg IL

H01L 3902, H01L 2328, H01L 2302, H01L 2944

357 80

An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternate version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process. The periphery and test points may be sheared away before the package is mounted to the PCB.

5436203, Jul 25, 1995

Jul 5, 1994

8/270602

Paul T. Lin - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2160

437209

A semiconductor (30) is shielded from electromagnetic interference by a combination of a reference plane (22) of a circuitized substrate (12) and two different encapsulants. The first encapsulant (38) is an electrically insulative encapsulant which mechanically protects a semiconductor die (32). The first encapsulant is constrained by a dam structure (40) so as not to encapsulate conductive reference pads (18) which are electrically connected to the reference plane by conductive vias (20). A second encapsulant (42) is dispensed over the first encapsulant and is in contact with the reference pads. The second encapsulant is an electrically conductive encapsulant, and is preferably made of a precursor material having the same or similar properties as that of the first encapsulant, but is filled with conductive filler particles to establish electrical conductivity of the encapsulant. Accordingly, the semiconductor die is effectively shielded from both the top and bottom by the electrically conductive encapsulant and the reference plane.

5468999, Nov 21, 1995

May 26, 1994

8/249602

Paul T. Lin - Austin TX
Michael B. McShane - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2302, H01L 2312, H01L 2348

257784

A ball grid array semiconductor device (10) includes a package substrate (14 or 16) having a plurality of conductive traces (18), bond posts (20), and conductive vias (22). A semiconductor die (12) is mounted to the package substrate. Orthogonal wire bonds (28) are used to electrically connect staggered bond pads (26) to corresponding bond posts (20) on the substrate. A liquid encapsulant (40) is used to cover the die, the wire bonds, and portions of the package substrate. In another embodiment, a package substrate (50) includes a lower bonding tier (52) and an upper bonding tier (54). Wire bonds (60) are used to electrically connect an outer row of bond pads (64) to bond posts (20) of lower tier (52), while wire bonds (62) are used to electrically connect an inner row of bond pads (64) to bond posts (20) of an upper tier (54). The loop height of wire bonds (60) is smaller than that of wire bonds (62).

5216278, Jun 1, 1993

Mar 2, 1992

7/841765

Paul T. Lin - Austin TX
Michael B. McShane - Austin TX
Howard P. Wilson - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2348, H01L 2944, H01L 2952, H01L 2960

257688

A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.

5036381, Jul 30, 1991

Jun 15, 1990

7/538629

Paul T. Lin - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2348, H01L 2944, H01L 2952, H01L 2960

357 70

The disclosed invention comprises multiple semiconductor devices within a single carrier structure. In accordance with one embodiment of the invention, a plurality of semiconductor die are coupled to the leads of a leadframe and are encapsulated by individual package bodies. A carrier structure is formed which encircles all of the die and encapsulates portions of the distal ends of the leads. The extreme distal portions of the leads extend through the carrier to form contact points which are used to access the semiconductor die. By having multiple devices within a single carrier, productivity is improved and costs associated with leadframe and carrier structure materials are reduced.

5378657, Jan 3, 1995

Mar 4, 1994

8/205424

Paul T. Lin - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2160

437217

A quad leadframe (22') for a CERQUAD is manufactured using conventional cladding and stamping technologies. A first metal layer (12) is provided with multiple cavities (14). A second metal layer (14) is clad to the first metal layer. A leadframe strip (22) can then be stamped from the clad metal. The leadframe has a leads (24) and bonding posts (28). The leads comprise two metal layers, and the bonding posts comprise only the second metal layer. The leadframe can then be used in the assembly of a semiconductor device (32). The portion of the leads external to the package body can be optionally etched to remove the second metal layer.