Paul Andrew Smith
Dentist in Colorado Springs, CO

5905744, May 18, 1999

Sep 30, 1997

8/940866

Brian G. Reise - Colorado Springs CO
Paul J. Smith - Colorado Springs CO

LSI Logic Corporation - Milpitas CA

G06H7/02

371 682

In a multifunction PCI device containing identical backend functions or other large, redundant functional blocks, a single backend function is selected as a primary function while in test mode. All backend I/O channels are then simultaneously tested in parallel, with the same data and control signals from a PCI local bus being driven to all backend channels during the same test clock cycle. A single backend channel is designated as the primary for providing requisite handshaking signals during output to the backend I/O channels. Input data from each backend channel is received in parallel and compared, with miscompares being flagged to allow testing of the input data path from the respective backend I/O channel. Only signals from the primary backend I/O channel are designated for transmission to the PCI local bus. Signals from the remaining backend channels are received in parallel with and compared to the signals from the primary channel, and miscompare flags are generated for any discrepancies identified.

7617428, Nov 10, 2009

Aug 23, 2006

11/508585

Paul J. Smith - Colorado Springs CO, US
Brad D. Besmer - Colorado Springs CO, US
Guy W. Kendall - Colorado Springs CO, US

LSI Corporation - Milpitas CA

G01R 31/28, G06F 7/02, G06F 13/24

714724, 714819, 710260

Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit design to permit dynamic, configurable interrupt generation from an integrated circuit based on conditions determined from monitoring of internal signals of the application circuit. The internal signals that may be tested and used to generate test interrupts are those not exposed to the external processor interface of the integrated circuit and thus may be configured to interrupt based on any internal state of the application specific functional circuits of the integrated circuit.

2013025, Oct 3, 2013

Mar 30, 2012

13/434954

Eugene Saghi - Colorado Springs CO, US
Paul J. Smith - Colorado Springs CO, US
Joshua P. Sinykin - Shrewsbury MA, US
Jeffrey K. Whitt - Colorado Springs CO, US

H03K 17/00

327403

Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit. The control unit receives the selected internal operational signals from the test signal routing hierarchy, and applies the selected internal operational signals to the external interface during normal operation of the integrated circuit.

2013026, Oct 3, 2013

Mar 30, 2012

13/434962

Paul J. Smith - Colorado Springs CO, US
Jeffrey K. Whitt - Colorado Springs CO, US
Eugene Saghi - Colorado Springs CO, US
Douglas J. Saxon - Colorado Springs CO, US
Joshua P. Sinykin - Shrewsbury MA, US

G06F 19/00, G06F 11/25, G01R 31/3177

714744, 702120, 714E11155

Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.