PATRICK S FERGUSON
Electrician at Detroit St, Houston, TX

6363439, Mar 26, 2002

Dec 7, 1998

09/206515

John D. Battles - Tomball TX
Paul B. Rawlins - Spring TX
Robert Allan Lester - Houston TX
Patrick L. Ferguson - Houston TX

Compaq Computer Corporation - Houston TX

G06F 1314

710 36, 710 45, 710106, 710107, 710110, 710117

A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units.

5506997, Apr 9, 1996

Jan 28, 1994

8/189078

David J. Maguire - Spring TX
Patrick L. Ferguson - Houston TX

Compaq Computer Corp. - Houston TX

G06F 1332, G06F 1314, G06F 1330

395800

A system for mapping a PCI interrupt signal to any EISA interrupt signal, in which sharing is allowed between PCI interrupts as well as between a PCI interrupt and an EISA interrupt. The actual mapping is performed during the Power On Self Test (POST) procedure, where the computer writes appropriate values into a set of MAP and MASK registers. Each MAP and MASK register corresponds to a PCI interrupt. Thus, by programming the appropriate MAP and MASK register to certain values, the corresponding PCI interrupt can be mapped to the desired EISA interrupt signal. A decode logic then produces a set of final interrupt signals based on the state of the PCI interrupt signals, the MAP and MASK registers, and the EISA interrupt signals. The final interrupt signals are provided to an interrupt controller, which responds to the assertion of the final interrupt signals by asserting an interrupt signal to the microprocessor.

5590378, Dec 31, 1996

Feb 1, 1996

8/593176

John S. Thayer - Houston TX
Patrick L. Ferguson - Houston TX

Compaq Computer Corporation - Houston TX

G06F 1200, G06F 1300

395850

A computer system which includes a DMA controller on the local I/O unit which can be programmed by either the host processor or the local processor. Semaphore flags and lock bits are provided to allow determination of control of the local DMA controller and for passing information. Additionally, data alignment and padding circuitry is provided. The circuitry is informed of the logical data arrangement desired or utilized by the host processor or other devices and knows the data arrangement of the local processor. The circuitry properly obtains and realigns the data based on the transfer direction and data arrangement. The circuitry further properly zero pads the data when realignment is such that padding is necessary.

5673397, Sep 30, 1997

Jul 29, 1996

8/681833

Patrick L. Ferguson - Houston TX
David J. Maguire - Spring TX

Compaq Computer Corporation - Houston TX

G06F 1300

395250

A FIFO queue is utilized to provide control information to the appropriate time slot in a time multiplexed serial link between an interface chip and a CODEC. The FIFO queue allows rewriting or replacement of any control registers present in the queue without requiring that a new entry be placed in the queue. A particular control register which is placed in the queue then maintains its place as the queue is emptied, even though the control register may be written one or more times while the control register entry is in the queue waiting for transmission to the CODEC. The loss of the prior command information is not a problem as the data rate of the serial link is still sufficiently high so that any minor transitory change which may have been desired would be of minimal effect in any regard and would have been inaudible to the human.

5596725, Jan 21, 1997

Feb 14, 1994

8/196586

Patrick L. Ferguson - Houston TX
David J. Maguire - Spring TX

Compaq Computer Corporation - Houston TX

G06F 1300

395250

A FIFO queue is utilized to provide control information to the appropriate time slot in a time multiplexed serial link between an interface chip and a CODEC. The FIFO queue allows rewriting or replacement of any control registers present in the queue without requiring that a new entry be placed in the queue. A particular control register which is placed in the queue then maintains its place as the queue is emptied, even though the control register may be written one or more times while the control register entry is in the queue waiting for transmission to the CODEC. The loss of the prior command information is not a problem as the data rate of the serial link is still sufficiently high so that any minor transitory change which may have been desired would be of minimal effect in any regard and would have been inaudible to the human.