PATRICK EVAN MAUPIN
Pilots at Southern Oaks Dr, Austin, TX
License number
Texas C1068329
Category
Airmen
Address
Address
2206 Southern Oaks Dr, Austin, TX 78745
Professional information
System For Transmitting And Receiving Digital Information Through Parallel Printer Port Of Computer By Using Embedding Strobe Bit In Eight Bit Data Of Printer Port
US Patent:
5581795, Dec 3, 1996
Filed:
Feb 28, 1996
Appl. No.:
8/608097
Inventors:
Patrick Maupin - Austin TX
Tom Martin - Austin TX
Tom Martin - Austin TX
Assignee:
Video Associates Labs, Inc. - Austin TX
International Classification:
G06F 1502
US Classification:
395882
Abstract:
A unique combination of software and hardware provides any computer with a system for high speed digital data communications using the computer's standard parallel printer port. The disclosed embodiment of the invention allows any computer with a standard parallel printer port to play or record digital audio sound allowing the computer to serve as a platform for multimedia presentations.
System For Transmitting And Receiving Combination Of Compressed Audio Information And Embedded Strobe Bit Between Computer And External Device Through Parallel Printer Port Of Computer
US Patent:
5819116, Oct 6, 1998
Filed:
Jul 30, 1996
Appl. No.:
8/688421
Inventors:
Patrick Maupin - Austin TX
Tom Martin - Austin TX
Tom Martin - Austin TX
Assignee:
Video Associates Labs, Inc. - Austin TX
International Classification:
G06F 1502
US Classification:
395888
Abstract:
A unique combination of software and hardware provides any computer with a system for high speed digital data communications using the computer's standard parallel printer port. The disclosed embodiment of the invention allows any computer with a standard parallel printer port to play or record digital audio sound allowing the computer to serve as a platform for multimedia presentations.
System For Transmitting And Receiving Combination Of Compressed Digital Information And Embedded Strobe Bit Between Computer And External Device Through Parallel Printer Port Of Computer
US Patent:
5652917, Jul 29, 1997
Filed:
Jul 30, 1996
Appl. No.:
8/690378
Inventors:
Patrick Maupin - Austin TX
Tom Martin - Austin TX
Tom Martin - Austin TX
Assignee:
Video Associates Labs, Inc. - Austin TX
International Classification:
G06F 1502
US Classification:
395888
Abstract:
A unique combination of software and hardware provides any computer with a system for high speed digital data communications using the computer's standard parallel printer port. The disclosed embodiment of the invention allows any computer with a standard parallel printer port to play or record digital audio sound allowing the computer to serve as a platform for multimedia presentations.
System For Transmitting And Receiving Digital Information Through Parallel Printer Port Of Computer By Using Embedding Strobe Bit In Eight Bit Data Of Printer Port
US Patent:
RE36647, Apr 4, 2000
Filed:
Dec 3, 1998
Appl. No.:
9/204937
Inventors:
Patrick Maupin - Austin TX
Tom Martin - Austin TX
Tom Martin - Austin TX
Assignee:
Video Associates Labs, Inc. - Austin TX
International Classification:
G06F 1502
US Classification:
710 8
Abstract:
A unique combination of software and hardware provides any computer with a system for high speed digital data communications using the computer's standard parallel printer port. The disclosed embodiment of the invention allows any computer with a standard parallel printer port to play or record digital audio sound allowing the computer to serve as a platform for multimedia presentations.
System For Transmitting And Receiving Combination Of Compressed Digital Information And Embedded Strobe Bit Between Computer And External Device Through Parallel Printer Port Of Computer
US Patent:
RE37118, Mar 27, 2001
Filed:
Jul 28, 1999
Appl. No.:
9/363219
Inventors:
Patrick Maupin - Austin TX
Tom Martin - Austin TX
Tom Martin - Austin TX
Assignee:
Video Associates Labs, Inc. - Austin TX
International Classification:
G06F15/02
US Classification:
710 68
Abstract:
A unique combination of software and hardware provides any computer with a system for high speed digital data communications using the computer's standard parallel printer port. The disclosed embodiment of the invention allows any computer with a standard parallel printer port to play or record digital audio sound allowing the computer to serve as a platform for multimedia presentations.
Patrick Maupin
Position:
SMTS Advanced Development at Microsemi
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Microsemi
since Oct 2011
-
SMTS Advanced Development
Skills:
SoC, Firmware, Debugging, ARM, Embedded Systems, Verilog, RTOS, USB, Processors, JTAG, Device Drivers, FPGA, Digital Signal Processors, Logic Analyzer, I2C, SPI, Embedded Software, Hardware Architecture, Python, C
System Having A Receive Data Register For Storing At Least Nine Data Bits Of Frame And Status Bits Indicating The Status Of Asynchronous Serial Receiver
US Patent:
5958024, Sep 28, 1999
Filed:
Aug 29, 1997
Appl. No.:
8/920930
Inventors:
Melanie D. Typaldos - Buda TX
Patrick E. Maupin - Austin TX
Patrick E. Maupin - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
G06F 1328, G06F 1342
US Classification:
710 26
Abstract:
An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data.
Emulator Support Mode For Disabling And Reconfiguring Timeouts Of A Watchdog Timer
US Patent:
6145103, Nov 7, 2000
Filed:
Apr 7, 1998
Appl. No.:
9/056509
Inventors:
Melanie D. Typaldos - Buda TX
Patrick E. Maupin - Austin TX
Patrick E. Maupin - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
S06F 1100
US Classification:
714 55
Abstract:
A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value.
Processing System, Memory And Methods For Use Therewith
US Patent:
7620792, Nov 17, 2009
Filed:
Aug 21, 2006
Appl. No.:
11/507650
Inventors:
Patrick Evan Maupin - Austin TX, US
Assignee:
Sigmatel, Inc. - Austin TX
International Classification:
G06F 12/02
US Classification:
711202, 714719, 714721
Abstract:
A memory includes an array of memory cells arranged in a plurality of rows and a plurality of columns. An address transform module receives a logical address including a logical column address and logical row address, and transforms the logical address into a physical address having a physical row address and a physical column address. An address decoder module accesses an individual memory cell of the array of memory cells based on the physical address.
Parallel Encoding/Decoding For Communications Protocol
US Patent:
2004015, Aug 5, 2004
Filed:
Mar 15, 2003
Appl. No.:
10/390536
Inventors:
Patrick Maupin - Austin TX, US
International Classification:
H04J003/00
US Classification:
370/476000
Abstract:
A set of a plurality of bits is processed by performing operations on the set of bits to produce a result that identifies whether the set of bits has a bit pattern and that identifies a location of the bit pattern in the set of bits. For a set of bits for an outgoing bitstream, one or more bits are inserted in the set of bits relative to the bit pattern if the set of bits has the bit pattern. For a set of bits for an incoming bitstream, one or more bits in the set of bits relative to the identified bit pattern are removed if the set of bits has the bit pattern and if the identified bit pattern comprises data bits.