NHAT NGUYEN
Pharmacy at Lawrence Expy, Santa Clara, CA

7183805, Feb 27, 2007

Mar 20, 2006

11/385234

Yueyong Wang - Sunnyvale CA, US
Barry W. Daly - Sunnyvale CA, US
Nhat M. Nguyen - San Jose CA, US
Yohan U. Frans - Palo Alto CA, US

Rambus Inc. - Los Altos CA

H03K 19/094

326 86, 326 83

Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

6539072, Mar 25, 2003

Mar 13, 2000

09/524402

Kevin S. Donnelly - San Francisco CA
Pak Shing Chau - San Jose CA
Mark A. Horowitz - Palo Alto CA
Thomas H. Lee - Cupertino CA
Mark G. Johnson - Los Altos CA
Benedict C. Lau - San Jose CA
Leung Yu - Santa Clara CA
Bruno W. Garlepp - Mountain View CA
Yiu-Fai Chan - Los Altos Hills CA
Jun Kim - Redwood City CA
Chanh Vi Tran - San Jose CA
Donald C. Stark - Palo Alto CA
Nhat M. Nguyen - San Jose CA

Rambus, Inc. - Los Altos CA

H04L 700

375371, 375358, 375373, 327158

Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock.

6696829, Feb 24, 2004

Nov 16, 2001

09/993929

Nhat M. Nguyen - San Jose CA
Kun-Yung K. Chang - Los Altos CA

Rambus Inc. - Los Altos CA

G01R 2312

324 7653, 324 7652, 324 7679

An integrated circuit device having a self-resetting phase-locked loop (PLL) circuit. The PLL circuit generates an output clock signal having a first frequency in a first operating mode and a second frequency in a second operating mode, the second frequency being determined, at least in part, by a reference clock signal. A control circuit within the integrated circuit resets the PLL circuit by selecting the first operating mode for a predetermined time interval, then selecting the second operating mode.

7248086, Jul 24, 2007

Mar 17, 2005

11/084438

Yohan Frans - Palo Alto CA, US
Nhat M. Nguyen - San Jose CA, US

Rambus, Inc. - Los Altos CA

H03L 7/06

327147, 327156

A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage across the replication capacitor is proportional to the control voltage of a voltage-controlled oscillator of the compensating phase-locked loop. A second embodiment generates the compensation current by controlling the voltage on the gate of a transistor. The gate voltage depends on charge added and subtracted by a charge pump in addition to the charge pumps in the loop filter. A third embodiment applies a leakage compensation circuit to a delay locked loop.

5379457, Jan 3, 1995

Jun 28, 1993

8/083449

Nhat M. Nguyen - San Jose CA

Hewlett-Packard Company - Palo Alto CA

H04B 128, G06G 702

455323

In a conventional Gilbert-cell active mixer, two local oscillator matched pairs of transistors receive a local oscillator input signal and are coupled to a radio frequency matched pair of transistors which receive a radio frequency input signal. The circuit generates an intermodulated output signal at the collectors of the local oscillator matched pairs. Noise degradation is reduced over the conventional mixer by replacing the standard radio frequency emitter degeneration resistor with a reactive element, thereby reducing thermal noise. Narrow-band input matching is achieved by insertion of a series inductive element and optional parallel capacitive element in line with the radio frequency input. Thermal noise contributed to the circuit is thereby minimized while circuit linearity is preserved in the narrow frequency band of interest.

5532655, Jul 2, 1996

Feb 24, 1995

8/393634

Nhat M. Nguyen - San Jose CA
Kevin J. Negus - Palo Alto CA

Hewlett-Packard Company - Palo Alto CA

H03H 102

333 1

A method for using the same input/output pin on an integrated circuit ("IC") for both a high frequency AC signal and a DC signal simultaneously and a first circuit means to accomplish this multiplexing is disclosed. The circuit topology comprises a first and second capacitor, coupled between the AC signal input and the AC signal output. A first and second resistor are coupled to the same input/output pin as the capacitors but between the two capacitors and respectively to a DC signal input and DC signal output. The DC signal path thus lies between the two capacitors and sees them as open circuits, while the AC signal path sees the two resistors as open circuits and the capacitors as short circuits.

6014042, Jan 11, 2000

Feb 19, 1998

9/025983

Nhat M. Nguyen - San Jose CA

Rambus Incorporated - Mountain View CA

H03K 526

327 3

A phase detector operating in a low voltage environment and providing a substantially constant integral voltage over variations in temperature, supply voltage and process parameters. The quadrature phase detector includes an equalizer, a switching unit, a sampler and comparator unit and a bias generator. The bias generator includes a switched capacitor structure which produces a bias current which tracks fluctuations in capacitance values due to temperature, supply voltage and process variations. The errors introduced due to fluctuations in bias current and capacitance are thus minimized.

7308065, Dec 11, 2007

Apr 18, 2006

11/406557

Kevin S. Donnelly - San Francisco CA, US
Pak Shing Chau - San Jose CA, US
Mark A. Horowitz - Palo Alto CA, US
Thomas H. Lee - Cupertino CA, US
Mark G. Johnson - Los Altos CA, US
Benedict C. Lau - San Jose CA, US
Leung Yu - Santa Clara CA, US
Bruno W. Garlepp - Mountain View CA, US
Yiu-Fai Chan - Los Altos Hills CA, US
Jun Kim - Redwood City CA, US
Chanh Vi Tran - San Jose CA, US
Donald C. Stark - Palo Alto CA, US
Nhat M. Nguyen - San Jose CA, US

Rambus Inc. - Los Altos CA

H03D 3/24, H03L 7/06

375373, 327149, 327158

A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.