Inventors:
Marcus L. Kornegay - Research Triangle Park NC, US
Ngan N. Pham - Research Triangle Park NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/08, G06F 12/00
US Classification:
711130, 711141, 711207, 711E12001, 711E12061, 711E12026, 711E12038
Abstract:
An apparatus, system, and method are disclosed for improving cache coherency processing. The method includes determining that a first processor in a multiprocessor system receives a cache miss. The method also includes determining whether an application associated with the cache miss is running on a single processor core and/or whether the application is running on two or more processor cores that share a cache. A cache coherency algorithm is executed in response to determining that the application associated with the cache miss is running on two or more processor cores that do not share a cache, and is skipped in response to determining that the application associated with the cache miss is running on one of a single processor core and two or more processor cores that share a cache.