NATHANAEL IAN GRIESERT
Pilots at Duggans Rd, Grass Valley, CA

7903058, Mar 8, 2011

Jan 21, 2005

11/041429

Florence Jacquet - Penn Valley CA, US
William J. McIntyre - Wheatland CA, US
Damian Swank - Rocklin CA, US
Nathanael Griesert - Grass Valley CA, US

National Semiconductor Corporation - Santa Clara CA

G09G 5/00

345 82, 345 86, 345207

A circuit and method for monitoring the forward voltage for a plurality of LEDs in a battery powered device so that the gain in the LED driver circuit can be switched at a point that optimizes the energy provided by the battery. The invention provides for sensing each LED's voltage, V, and determining the maximum forward voltage, V, between the plurality of LEDs. The invention uses the knowledge of Vin conjunction with V, converter output resistance and LED current, and current source/sink minimum headroom to switch from an initial gain to some higher gain just before the current sinks/sources would drop out, or from a higher gain to a lower gain in the event of the battery voltage going back to a voltage close to its initial value after being momentarily pulled down by a heavy load.

8018215, Sep 13, 2011

Jun 26, 2008

12/147427

Nathanael Griesert - Grass Valley CA, US
Damian Swank - Rocklin CA, US

National Semiconductor Corporation - Santa Clara CA

G05F 1/40

323282, 323224, 363 89

A circuit for monitoring the inductance value of a switching regulator is provided. The circuit includes an inductance sensor circuit that is coupled to a switch node of a switching regulator. The inductor sensor circuit includes a switch, a ramp circuit, and a comparison circuit. The switch is arranged to receive a switch control signal that is based, at least in part, on a switching signal of the switching regulator. When the switch control signal is asserted, the comparison circuit receives a comparison input voltage that is based, at least in part, on the inductance value of the switching regulator. The comparison circuit compares the comparison input voltage to a ramp voltage of the ramp circuit and outputs a signal indicative of whether the inductance value of the switching regulator is at or below a predetermined threshold inductance value.

7271626, Sep 18, 2007

Oct 27, 2004

10/974177

Alexander Burinskiy - San Jose CA, US
Nathanael Griesert - Grass Valley CA, US
Arun Rao - Rocklin CA, US
William J. McIntyre - Wheatland CA, US
John Philip Parry - Grass Valley CA, US

National Semiconductor Corporation - Santa Clara CA

H03K 3/00

327108, 327379

A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor circuit with a gating signal that is delayed by each buffer. Optionally, the voltage of the gating signal can be varied. Each transistor stage may comprise one or more transistors in parallel. A switched capacitor DC/DC converter incorporating the multi-stage transistor circuit is provided in which parasitic ringing at the output is substantially reduced or eliminated. Additionally, the multi-stage transistor circuit is well suited for implementing an adaptive non-overlapping gating signal generator for complementarily driving a series arrangement of multi-stage transistors. An adaptive gating signal generator incorporating the multi-stage transistor circuit provides the minimum dead time between the gating signals that will ensure under all conditions that the multi-stage transistors will not be on at the same time.

7456677, Nov 25, 2008

May 1, 2006

11/381101

Arun Rao - Rocklin CA, US
John Philip Parry - Grass Valley CA, US
William J. McIntyre - Wheatland CA, US
Nathanael Griesert - Grass Valley CA, US

National Semiconductor Corporation - Santa Clara CA

G05F 1/10

327536, 327538

A switch array circuit that enables voltage regulation by bucking a relatively larger input voltage as it declines over time with different fractional gains that are based on different gain phase arrangements for a plurality of capacitors. A common rest phase is provided during the switching between the different gain phases. The rest phase inherently enables power to be conserved during gain transitions. Increasingly larger fractional gain phases (less buck) is provided as the input voltage declines over time, e. g. , from ⅓ to ⅖ to ½ to ⅔ to unity, and the like. Also, the common rest phase for the plurality of capacitors is arranged to minimize fluctuation of the output voltage during switching between phases to generate a selected gain from the gain phase. Additionally, the common rest phase conserves/stores energy during switching transitions between multiple gain phases. The stored energy in the common rest phase can be subsequently reused in the gain phases.

7573252, Aug 11, 2009

Jun 7, 2004

10/862225

Nathanael Griesert - Grass Valley CA, US

National Semiconductor Corporation - Santa Clara CA

G05F 3/26

323315, 323901, 363 49

A method and circuit for providing a controlled ramping and filtering to a reference voltage in a regulator circuit such that an inrush current is limited and noise coupling to an output voltage is reduced. In a typical regulator circuit a soft-start and filter circuit is inserted between a feedback amplifier and a charge transfer circuit. The soft-start and filter circuit comprises a pair of transistors that are arranged to operate as a current mirror, a biasing current source determining the current drawn from the current mirror, and a soft-start capacitor shunted by a third transistor providing a conditioned reference voltage. When reference voltage rises rapidly during power-up, charging of the soft-start capacitor with constant current provides a soft-sloped conditioned reference voltage. In steady state, soft-start capacitor and a resistance of the transistor provide a first order low pass filter reducing noise that couples to the reference voltage.

7991282, Aug 2, 2011

Dec 8, 2008

12/330448

William J. McIntyre - Wheatland CA, US
John Philip Parry - Grass Valley CA, US
Nathanael Griesert - Grass Valley CA, US

National Semiconductor Corporation - Santa Clara CA

G03B 7/26, H05B 37/00

396205, 315241 P, 315241 S

A circuit and method for charging a super capacitor to an optimal voltage that provides a desired flash diode current value while minimizing power dissipation in circuit elements other than the flash diode. One embodiment uses periodic sampling of the current through the flash diode and termination of the charging upon the super capacitor having been charged to a voltage value that produces the desired flash diode current. Another embodiment includes a current regulator in the flash diode firing circuit that keeps the current at a substantially constant level during the time that the flash diode is being fired.