NAM HOON KIM, D.C.
Chiropractic at Stark St, Portland, OR

2008008, Apr 3, 2008

Sep 27, 2006

11/527782

Muhammad M. Khellah - Tigard OR, US
Dinesh Somasekhar - Portland OR, US
Yibin Ye - Portland OR, US
Nam Sung Kim - Portland OR, US
Vivek K. De - Beaverton OR, US

G11C 7/00, G11C 5/14

36518911, 36518909

A memory line driver system may include a first input line to receive a clock-gated signal associated with a first supply power level, a second input line to receive an information signal associated with a second supply power level, and an output to drive a memory cell line according to the first supply power level based on the clock-gated signal and the information signal.

2009000, Jan 1, 2009

Jun 27, 2007

11/823358

Min Huang - Cupertino CA, US
Chris Wilkerson - Portland OR, US
Nam Sung Kim - Portland OR, US
Moinuddin K. Qureshi - Austin TX, US

G06F 12/00

711114

A method for improving performance of a digital memory array device including a plurality of memory cells; each respective memory cell storing a first digital value and a second digital value being an inverse of the first digital value; storing of the first and second digital values being controlled by a first digital signal effecting selection of a specified memory cell for storing; includes: (a) determining an extant value relating to the first digital signal; (b) if the extant value has a first value, effecting a bit flip operation in the specified memory cell to invert values of at least one of the stored first digital and the second digital values; (c) if the extant value does not have the first value, foregoing the bit flip operation in the specified memory cell.

7558097, Jul 7, 2009

Dec 28, 2006

11/648399

Muhammad M. Khellah - Tigard OR, US
Dinesh Somasekhar - Portland OR, US
Yibin Ye - Portland OR, US
Nam Sung Kim - Portland OR, US
Vivek De - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C 5/06

365 63, 365154

For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

7653846, Jan 26, 2010

Dec 28, 2006

11/648490

Nam Sung Kim - Portland OR, US
Yibin Ye - Portland OR, US
Dinesh Somasekhar - Portland OR, US
Vivek De - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C 29/00

714718

For one embodiment, an apparatus may include a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also include first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments include other apparatuses, methods, and systems.

7653850, Jan 26, 2010

Jun 5, 2007

11/758124

James W. Tschanz - Portland OR, US
Keith A. Bowman - Hillsboro OR, US
Nam Sung Kim - Portland OR, US
Chris Wilkerson - Portland OR, US
Shih-Lien L. Lu - Portland OR, US
Tanay Karnik - Portland OR, US

Intel Corporation - Santa Clara CA

G01R 31/28, G06K 5/04

714726, 714699

Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.

2008016, Jul 3, 2008

Dec 29, 2006

11/648297

Nam Sung Kim - Portland OR, US
Muhammad M. Khellah - Tigard OR, US
Vivek De - Beaverton OR, US

G06F 12/02

711216

For one disclosed embodiment, an apparatus may comprise cache memory circuitry including multiple portions of destructive read memory cells and access control circuitry to access portions of destructive read memory cells. The apparatus may also comprise address hash logic to receive an address and to generate a hashed address based at least in part on at least a portion of the received address using a hashing technique to help distribute accesses by the access control circuitry across different portions of destructive read memory cells. Other embodiments are also disclosed.

7812631, Oct 12, 2010

Dec 12, 2006

11/609823

Nam Sung Kim - Portland OR, US
Vivek De - Beaverton OR, US

Intel Corporation - Santa Clara CA

H03K 17/16, H03K 19/003

326 21, 326 40, 326 34, 327544, 365227

In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.

7532528, May 12, 2009

Jun 30, 2007

11/772151

Dinesh Somasekhar - Portland OR, US
Muhammad M Khellah - Tigard OR, US
Yibin Ye - Portland OR, US
Nam Sung Kim - Portland OR, US
Vivek K De - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C 7/00

365205, 365 63, 36518908

A memory system having a selectable configuration for sense amplifiers is included. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.

2007027, Nov 22, 2007

May 17, 2006

11/435701

Nam Sung Kim - Portland OR, US
Shih-Lien L. Lu - Portland OR, US
Chris Wilkerson - Portland OR, US
Edward Grochowski - San Jose CA, US

G06F 13/00

711154

Methods and apparatus to reduce aging effect on memory are described. In one embodiment, a modified version of data is stored in a portion of a storage unit during a first time period.