MOHAMMAD A YUNUS
Medical Practice at Blackburn St, Dallas, TX

6734567, May 11, 2004

Aug 23, 2002

10/226415

Mohammad Yunus - Dallas TX

Texas Instruments Incorporated - Dallas TX

H01L 2348

257778, 257688, 257737, 257783, 257788, 257792, 257795

Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a surface. Using a layer of polymeric material, the chip surface is mounted on the substrate surface. The polymeric material protrudes beyond the chip periphery and spreads some distance along the substrate surface. A metal layer is on the substrate surface, this layer is shaped as a band around the chip periphery; the band has an inner edge near the chip periphery, and an outer edge near the contour of the polymer protrusion. This metal band serves as a guard ring to stop any nascent crack propagating in the polymer protrusion.

6696757, Feb 24, 2004

Jun 24, 2002

10/178138

Mohammad Yunus - Dallas TX
Anthony L. Coyle - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 2348

257735, 257696, 257738, 257758, 257778, 257784

A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

2003020, Nov 6, 2003

May 3, 2002

10/138392

Mohammad Yunus - Dallas TX, US

H01L023/06

257/684000

A method for assembling FCBGA packages having fewer heating cycles and process steps than prior art is made possible through the use of a novel carrier pallet. The pallet includes recesses which mirror external solder ball contacts of the BGA package under assembly. A solder ball is positioned in each recess, a chip carrier substrate aligned and positioned atop the solder, a chip having flip chip contacts aligned to the opposite surface of the chip carrier, and the assemblage subjected to heating and cooling as required to connect both sets of contacts in a single thermal cycle. As required by the device under assembly, an underfill material and a protective cover may be included in the assembly process while making use of the carrier pallet, and without moving the devices. The carrier pallet may be used for transporting and attaching solder contacts of many types of BGA or CSP devices. Yield, reliability, and cost advantages are made possible by the invention.

7550314, Jun 23, 2009

Mar 13, 2006

11/374496

Charles Anthony Odegard - McKinney TX, US
Mohammad Yunus - Dallas TX, US
Ferdinand Borromeo Arabe - Baguio, PH

Texas Instruments Incorporated - Dallas TX

H01L 21/00

438106, 438108

A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

7045904, May 16, 2006

Dec 10, 2003

10/732567

Charles Anthony Odegard - McKinney TX, US
Mohammad Yunus - Dallas TX, US
Ferdinand Borromeo Arabe - Baguio, PH

Texas Instruments Incorporated - Dallas TX

H01L 29/40

257787, 257778

A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

6933173, Aug 23, 2005

May 30, 2003

10/448843

Mohammad Yunus - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H01L021/48, H01L021/50

438110, 438108, 438113, 438127

According to one embodiment of the invention, a method of packaging flip chips includes providing a plurality of flip chips and a panel, forming a plurality of partitions outwardly from the panel, coupling the flip chips to the panel such that each partition surrounds a respective flip chip, and forming an underfill region between each of the flip chips and the panel. Each partition prevents a respective underfill region from engaging an adjacent underfill region.

6907151, Jun 14, 2005

Sep 24, 2002

10/253087

Mohammad Yunus - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

G02B006/12

385 14, 385 31

A flip chip optoelectronic device assembly includes a hollow, cylindrical spacer between an optical source in the substrate and the active surface of the chip, which precludes attenuation of the signal and allows direct transmission through air. An underfill material fills the space between chip and substrate, thereby allowing substrates which are not necessarily matched in thermal expansion to the chips, and the spacer acts as a dam to prevent ingress of underfill material into the optical path. The spacer not only allows use of conventional underfill materials to support the interconnection joints and thermal mismatch, but also defines a fixed “z” axis distance between substrate and chip.

2004015, Aug 5, 2004

Jan 20, 2004

10/762163

Mohammad Yunus - Dallas TX, US
Anthony Coyle - Plano TX, US

H01L023/48, H01L023/52, H01L029/40

257/735000

A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.