DR. MINH TRAN, D.C
Chiropractic at Atherton Ave, San Jose, CA

6674953, Jan 6, 2004

Jan 2, 2002

10/038079

Zhupei Shi - San Jose CA
Tongxin Lu - San Jose CA
Minh Tran - San Jose CA
Jerry Lee - Saratoga CA

Alliance Fiber Optic Products, Inc. - Sunnyvale CA

G02B 600

385140, 359484, 359629, 385134

A controllable attenuator includes a pair of collimators respectively connected to input and output fibers. A pair of reflection devices are respectively positioned behind the pair of collimators opposite to the corresponding input and output fibers. A U-like light path is defined among the pair of collimators and the pair of reflection devices. A neutral density filter is moveably positioned between the pair of reflection devices wherein a moving direction of the filter is preferably parallel to a longitudinal direction of the pair of collimators. An ND filter position indicator such as a potentiometer, is used to dynamically monitor attenuation setting.

6348732, Feb 19, 2002

Nov 18, 2000

09/715702

Sergey D. Lopatin - Santa Clara CA
Minh Van Ngo - Fremont CA
Minh Quoc Tran - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2348

257751, 257750, 257758

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

6425991, Jul 30, 2002

Oct 2, 2000

09/678182

Minh Quoc Tran - San Jose CA
Christy Mei-Chu Woo - Cupertino CA

Advanced Micro Devices, Inc. - Sunnyvale CA

C25D 1700

204224R, 204267, 2042307

An electroplating system is provided for seed layer covered semiconductor wafers. A plating chamber is provided with an inert primary anode connectible to a positive voltage source and a semiconductor wafer connector connectible to a negative voltage source. The plating chamber further contains a consumable ring secondary anode connectible to the positive voltage source such that, when the plating chamber is filled with a plating solution and a semiconductor wafer is connected to the semiconductor wafer connector and the voltages are connected, the seed layer on the semiconductor wafer will be plated by consuming the consumable ring secondary anode.

2009022, Sep 3, 2009

Feb 29, 2008

12/040593

James Yu - San Francisco CA, US
Minh Tran - San Jose CA, US

Broadcom Corporation - Irvine CA

G06F 1/26

713300

An active powered device (PD) for the application of power over Ethernet (PoE). In a fixed power budget environment, it is important for the power sourcing equipment (PSE) to accurately determine a power budget for the various powered ports. An active PD can be designed to gather additional information (e.g., current and input voltage) during PD operation and to forward the additional information to the PSE. The PSE can then use the additional information to adjust operational parameters such as a power budget.

8044747, Oct 25, 2011

Apr 30, 2009

12/433080

James Yu - San Francisco CA, US
Minh Tran - San Jose CA, US

Broadcom Corporation - Irvine CA

H03H 2/00, H04B 3/00

333 24R, 375257

A system and method for enabling power applications over a single conductor pair. In one embodiment, data transformers are coupled to a single conductor pair using one or more direct current (DC) blocking elements that preserve an alternating current path. Power is injected onto the single conductor pair after the DC blocking elements and power is extracted from the single conductor pair before the DC blocking elements. Saturation of the data transformers by the injection of power onto the single pair is thereby prevented.