MINESH D PATEL
Medical Practice at Michael Tiago Cir, Maitland, FL

License number
Florida 115915
Issued Date
Apr 30, 2013
Effective Date
Feb 1, 2017
Expiration Date
Jan 31, 2017
Category
Health Care
Type
Medical Doctor
Address
Address 2
2046 Michael Tiago Cir, Maitland, FL 32751
1400 S Orange Ave, Orlando, FL 32806
Phone
(334) 220-0953

Personal information

See more information about MINESH D PATEL at radaris.com
Name
Address
Phone
Minesh Patel
4400 NW 39Th Ave, Gainesville, FL 32606
(352) 362-2738
Minesh Patel, age 47
4010 61St Ave E, Bradenton, FL 34203
(941) 752-1509
Minesh Patel
3154 SE Monte Vista Ct, Port St Lucie, FL 34952
Minesh Patel
3010 SW 20Th St, Ocala, FL 34474
(352) 237-8958
Minesh Patel, age 56
3015 W Bay View Ave, Tampa, FL 33611

Professional information

See more information about MINESH D PATEL at trustoria.com
Minesh Patel Photo 1
Pm For Oreo At First National Bank Of Central Florida

Pm For Oreo At First National Bank Of Central Florida

Position:
PM for OREO at First National Bank of Central Florida
Location:
Orlando, Florida Area
Industry:
Banking
Work:
First National Bank of Central Florida - PM for OREO


Minesh Patel Photo 2
Svp At Anglo Investments

Svp At Anglo Investments

Position:
svp at anglo investments
Location:
Orlando, Florida Area
Industry:
Real Estate
Work:
anglo investments - svp


Minesh Patel Photo 3
Method Of Creating Hydrogen Isotope Reservoirs In A Semiconductor Device

Method Of Creating Hydrogen Isotope Reservoirs In A Semiconductor Device

US Patent:
6605529, Aug 12, 2003
Filed:
May 11, 2001
Appl. No.:
09/853317
Inventors:
Sundar Chetlur - Singapore, SG
Jennifer M. McKinley - Orlando FL
Minesh A. Patel - Orlando FL
Pradip K. Roy - Orlando FL
Jonathan Zhong-Ning Zhou - Orlando FL
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 214763
US Classification:
438627, 438585, 438643, 438795
Abstract:
The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.


Minesh Patel Photo 4
Method Of Determining A Trap Density Of A Semiconductor/Oxide Interface By A Contactless Charge Technique

Method Of Determining A Trap Density Of A Semiconductor/Oxide Interface By A Contactless Charge Technique

US Patent:
6391668, May 21, 2002
Filed:
May 1, 2000
Appl. No.:
09/562346
Inventors:
Carlos M. Chacon - Orlando FL
Sundar S. Chetlur - Orlando FL
Brian E. Harding - Orlando FL
Minesh A. Patel - Orlando FL
Pradip K. Roy - Orlando FL
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
H01L 2166
US Classification:
438 17, 438197, 324769
Abstract:
The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.


Minesh Patel Photo 5
Methods For Deuterium Sintering

Methods For Deuterium Sintering

US Patent:
6576522, Jun 10, 2003
Filed:
Dec 8, 2000
Appl. No.:
09/733570
Inventors:
Sundar Srinivasan Chetlur - Singapore, SG
Pradip Kumar Roy - Orlando FL
Minesh Amrat Patel - Orlando FL
Sidhartha Sen - Singapore, SG
Vivek Saxena - Orlando FL
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 21336
US Classification:
438359, 438660, 438795
Abstract:
A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.


Minesh Patel Photo 6
Silicon-Rich Low Thermal Budget Silicon Nitride For Integrated Circuits

Silicon-Rich Low Thermal Budget Silicon Nitride For Integrated Circuits

US Patent:
6940151, Sep 6, 2005
Filed:
Sep 30, 2002
Appl. No.:
10/261463
Inventors:
Michael Scott Carroll - Orlando FL, US
Yi Ma - Santa Clara CA, US
Minesh Amrat Patel - Orlando FL, US
Peyman Sana - Orlando FL, US
Assignee:
Agere Systems, Inc. - Allentown PA
International Classification:
H01L031/0392
US Classification:
257649, 257636, 257630, 257640
Abstract:
A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si—H bonds being at least 1. 5 times as great as a concentration of hydrogen in N—H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.


Minesh Patel Photo 7
Method Of Forming A Liner For Tungsten Plugs

Method Of Forming A Liner For Tungsten Plugs

US Patent:
2003009, May 15, 2003
Filed:
Nov 15, 2001
Appl. No.:
09/999285
Inventors:
Siddhartha Bhowmik - Allentown PA, US
Sailesh Merchant - Orlando FL, US
Minesh Patel - Orlando FL, US
Darrell Simpson - Gotha FL, US
International Classification:
B32B009/00, B05D003/04, C23C016/00, B05D003/02
US Classification:
428/698000, 428/336000, 428/469000, 428/472000, 427/376100, 427/248100, 427/378000
Abstract:
A liner and method of forming a liner for a tungsten plug in a semiconductor device which reduces cost and improves reliability. In one aspect, it has been discovered that by depositing an initial film of titanium using any conventional process such as CVD, PVD or IMP (ion metal plasma) and then heating the device in a nitrogen atmosphere to a temperature of about 450 degrees C., a thin protective layer of titanium nitride can be form on the surface of the initial film. The protective layer has been found to be uniform in density and avoids the irregularities occurring in deposited titanium nitride. The thickness of the TiN layer can be controlled by controlling the time duration of the annealing process and by controlling the pressure of the nitrogen in the annealing tool. Using this two step method, the integrity of the titanium nitride layer is preserved and the formation of volcanoes is avoided.