MIGUEL A DELGADO
Electrician at Bigmouth Hook, San Antonio, TX

5943591, Aug 24, 1999

Jul 10, 1997

8/890910

Edward R. Vokoun - Boerne TX
Miguel A. Delgado - San Antonio TX
Gregory N. Carter - San Antonio TX
Brian D. Richardson - Saratoga CA
Rajive Dhar - Santa Clara CA
Elizabeth A. Chambers - Mountain View CA

VLSI Technology - San Jose CA

H01L 21301

438462

A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

5686171, Nov 11, 1997

Dec 30, 1993

8/176353

Edward R. Vokoun - Boerne TX
Miguel A. Delgado - San Antonio TX
Gregory N. Carter - San Antonio TX
Brian D. Richardson - Saratoga CA
Rajive Dhar - Santa Clara CA
Elizabeth A. Chambers - Mountain View CA

VLSI Technology, Inc. - San Jose CA

B32B 900

428209

A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

5789795, Aug 4, 1998

Dec 28, 1995

8/579824

Ivan Sanchez - San Antonio TX
Yu-Pin Han - Dallas TX
Miguel A. Delgado - San Antonio TX

VLSI Technology, Inc. - San Jose CA

H01L 2900

257530

An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

5387311, Feb 7, 1995

Feb 16, 1993

8/017542

Stacy W. Hall - San Antonio TX
Miguel A. Delgado - San Antonio TX

VLSI Technology, Inc. - San Jose CA

H01L 21306

156630

A method for removing excess spacer material in the link vias and open areas of an anti-fuse structure without thinning the anti-fuse layer in the vias by overetching. In an anti-fuse structure, a spacer layer is deposited on an anti-fuse layer where vias in the structure cause a thinner layer of spacer material to be deposited in the vias. A first etch of the spacer layer is accomplished to provide protective spacers in the vias. The etch completely removes the thinner section of the spacer material between the spacers in the vias without overetch, while some spacer material portions remain on the other, open areas of the anti-fuse structure. Designated fuse vias are masked and a second etch of the leftover spacer material is accomplished. This method removes excess spacer material from link vias and other areas around the fuse vias and prevents the anti-fuse layer in the fuse vias from thinning from overetching procedures.

6156588, Dec 5, 2000

Jun 23, 1998

9/102367

Ivan Sanchez - San Antonio TX
Miguel A. Delgado - San Antonio TX

VLSI Technology, Inc. - San Jose CA

H01L 2182

438131

The invention relates generally to integrated circuits and, in particular, to methods of forming anti-fuse structures during integrated circuit manufacture. In an exemplary embodiment of the invention, a conductive base layer is formed over a semiconductor substrate. An insulating layer is formed on the conductive base layer and is patterned to expose a portion of the conductive base layer. An anti-fuse layer is formed on the insulating layer and the exposed portion of the conductive base layer. A conductive protection layer is formed on the anti-fuse layer. An anti-fuse island is formed by sequentially removing a portion of the conductive protection layer, and underlying portions of the anti-fuse layer and the insulating layer. The conductive base layer is patterned after forming the anti-fuse island. The invention provides a simplified method for the formation of anti-fuse structures which is compatible with submicron device geometries.

5433238, Jul 18, 1995

Sep 6, 1994

8/300935

Stephen Cannizzaro - Boise ID
John Cain - Schertz TX
Miguel Delgado - San Antonio TX
Ramiro Solis - San Antonio TX

VLSI Technology, Inc. - San Jose CA

B65B 3104

137 14

A system for evacuating a reactor chamber includes a main evacuation line connected at one end thereof to the reactor chamber and at another end thereof to a means for creating a partial vacuum. A valve in the main evacuation line divides the line into a chamber side and a vacuum side. A second line is connected at one end to the vacuum side of the main evacuation line and at another end to a fluid supply source. As the valve in the main evacuation line is opened, fluid is supplied through the second line to the main evacuation line to prevent rapid, turbulence-inducing pressure drops in the reactor chamber.