MICHELE BETHANY BOLAND
Pilots at Fairview Ave, Seattle, WA

License number
Washington A3773274
Issued Date
Feb 2016
Expiration Date
Feb 2018
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
2201 Fairview Ave E APT 5, Seattle, WA 98102

Professional information

Michele Boland Photo 1

Senior Development Manager At Prowess

Location:
Greater Seattle Area
Industry:
Computer Software
Work:
Prowess - Greater Seattle Area Oct 2012 - Aug 2013 - Lead Technical Program Manager Teleion Consulting Apr 2011 - Oct 2012 - Senior Technical Program Manager Research In Motion Jan 2009 - Jun 2011 - Technical Product Manager Eve Online 2009 - 2009 - CSM 2/CSM 3/CSM 7 Vulcan Capital Management Sep 2008 - Dec 2008 - Program Manager P2 Solutions Oct 2007 - Sep 2008 - Program Manager Microsoft Jun 2005 - Sep 2007 - Program Manager Intrinsyc Software Feb 2005 - Jun 2005 - Program Manager Motorola Sep 2003 - Feb 2005 - Lead Program Manager General Software Aug 2002 - Sep 2003 - Developer Microsoft Dec 1997 - Dec 2001 - Senior Program Manager Motorola Aug 1995 - Dec 1997 - Senior Systems Architect Compaq Nov 1993 - Aug 1995 - Systems Engineer III SAIL Software Jan 1980 - Jun 1992 - Owner
Education:
Arizona State University 1976 - 1981
Scottsdale Community College 1974 - 1976
Interests:
Aviation, Sailing, Guitar, Bass, R/C Flying, Computer Gaming, Interactive Electronic Art, Antique electronics, old computers


Michele Boland Photo 2

Systems And Methods For Providing Intermediate Targets In A Graphics System

US Patent:
2003002, Jan 30, 2003
Filed:
Jul 16, 2002
Appl. No.:
10/196864
Inventors:
Michele Boland - Seattle WA, US
Charles Boyd - Woodinville WA, US
Anantha Kancherla - Redmond WA, US
International Classification:
G09G005/00
US Classification:
345/700000
Abstract:
Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system are provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modem graphics chips.


Michele Boland Photo 3

Systems And Methods For Providing Intermediate Targets In A Graphics System

US Patent:
8063909, Nov 22, 2011
Filed:
Jun 22, 2009
Appl. No.:
12/489316
Inventors:
Michele B Boland - Seattle WA, US
Charles N Boyd - Woodinville WA, US
Anantha R Kancherla - Redmond WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06T 1/00
US Classification:
345522, 345426, 345543, 345505, 712 1, 717120, 717131
Abstract:
Intermediate target(s) are utilized in connection with computer graphics in a computer system. In various embodiments, intermediate memory buffers in video memory are utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i. e. , the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.


Michele Boland Photo 4

Systems And Methods For Providing Intermediate Targets In A Graphics System

US Patent:
8379035, Feb 19, 2013
Filed:
Oct 31, 2011
Appl. No.:
13/286054
Inventors:
Michele B Boland - Seattle WA, US
Charles N Boyd - Woodinville WA, US
Anantha R Kancherla - Redmond WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06T 11/40
US Classification:
345552, 345421, 345582, 345543, 717120, 717131
Abstract:
Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i. e. , the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.


Michele Boland Photo 5

Systems And Methods For Downloading Algorithmic Elements To A Coprocessor And Corresponding Techniques

US Patent:
2005012, Jun 9, 2005
Filed:
Nov 12, 2004
Appl. No.:
10/987686
Inventors:
Charles Boyd - Woodinville WA, US
Michele Boland - Seattle WA, US
Michael Toelle - Bellevue WA, US
Anantha Kancherla - Redmond WA, US
Amar Patel - Redmond WA, US
Iouri Tarassov - Bellevue WA, US
Stephen Wright - Bothell WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06F013/14
US Classification:
345520000
Abstract:
Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.


Michele Boland Photo 6

Systems And Methods For Downloading Algorithmic Elements To A Coprocessor And Corresponding Techniques

US Patent:
7978197, Jul 12, 2011
Filed:
Nov 12, 2004
Appl. No.:
10/987144
Inventors:
Charles N. Boyd - Woodinville WA, US
Michele B. Boland - Seattle WA, US
Michael A. Toelle - Bellevue WA, US
Anantha Rao Kancherla - Redmond WA, US
Amar Patel - Redmond WA, US
Iouri Tarassov - Bellevue WA, US
Stephen H. Wright - Bothell WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06T 1/20, G06F 15/76
US Classification:
345522
Abstract:
Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.


Michele Boland Photo 7

Systems And Methods For Downloading Algorithmic Elements To A Coprocessor And Corresponding Techniques

US Patent:
8035646, Oct 11, 2011
Filed:
Nov 12, 2004
Appl. No.:
10/987120
Inventors:
Charles N. Boyd - Woodinville WA, US
Michele B. Boland - Seattle WA, US
Michael A. Toelle - Bellevue WA, US
Anantha Rao Kancherla - Redmond WA, US
Amar Patel - Redmond WA, US
Iouri Tarassov - Bellevue WA, US
Stephen H. Wright - Bothell WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06T 1/00
US Classification:
345522
Abstract:
Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.


Michele Boland Photo 8

Systems And Methods For Downloading Algorithmic Elements To A Coprocessor And Corresponding Techniques

US Patent:
8274517, Sep 25, 2012
Filed:
Nov 12, 2004
Appl. No.:
10/986586
Inventors:
Charles N. Boyd - Woodinville WA, US
Michele B. Boland - Seattle WA, US
Michael A. Toelle - Bellevue WA, US
Anantha Rao Kancherla - Redmond WA, US
Amar Patel - Redmond WA, US
Iouri Tarassov - Bellevue WA, US
Stephen H. Wright - Bothell WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06T 1/00, G06T 15/00
US Classification:
345522
Abstract:
Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.


Michele Boland Photo 9

Systems And Methods For Downloading Algorithmic Elements To A Coprocessor And Corresponding Techniques

US Patent:
8305381, Nov 6, 2012
Filed:
Apr 30, 2008
Appl. No.:
12/112676
Inventors:
Charles N. Boyd - Woodinville WA, US
Michele B. Boland - Seattle WA, US
Michael A. Toelle - Bellevue WA, US
Anantha Rao Kancherla - Redmond WA, US
Amar Patel - Redmond WA, US
Iouri Tarassov - Bellevue WA, US
Stephen H. Wright - Bothell WA, US
Assignee:
Microsoft Corporation - Redmond WA
International Classification:
G06T 1/00, G06F 13/14, G09G 5/00
US Classification:
345522, 345520, 345582
Abstract:
Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders.


Michele Boland Photo 10

Apparatus, And Associated Method, For Assigning Policy Settings To A Mobile Station

US Patent:
2011026, Oct 27, 2011
Filed:
Apr 24, 2010
Appl. No.:
12/766876
Inventors:
Michele Bethany Boland - Seattle WA, US
David MacKlem - Mississauga, CA
Keith Alwyn Watson - Mississauga, CA
Kenneth Cyril Schneider - Waterloo, CA
Peter L. Mitchelmore - Elk Grove CA, US
Jeffrey John Holleran - Viera FL, US
Assignee:
RESEARCH IN MOTION LIMITED - WATERLOO
International Classification:
H04W 4/08
US Classification:
455418
Abstract:
An apparatus, and an associated method, automatically calculates and assigns policy settings to be implemented at mobile stations. Information is collected relating to groups, such as groups within an enterprise, to which users of the mobile stations are members. Policy-setting conflicts between different groups, if the user is a member of more than one group, are reconciled, and the policy settings that are assigned are of reconciled settings.