MICHAEL ZHENG-REN HSING
Pilots at Great Oaks Blvd, San Jose, CA
License number
California A4621584
Issued Date
Nov 2015
Expiration Date
Nov 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
79 Great Oaks Blvd, San Jose, CA 95119
Personal information
See more information about MICHAEL ZHENG-REN HSING at radaris.comName
Address
Phone
17106 Devonshire St, Northridge, CA 91325
17943 Chatsworth St, Granada Hills, CA 91344
3243 Montelena Dr, San Jose, CA 95135
519 Camino Verde, South Pasadena, CA 91030
730 Tender Ln, Foster City, CA 94404
Professional information
Technique Of Password Encryption And Decryption For User Authentication In A Federated Content Management System
US Patent:
6735310, May 11, 2004
Filed:
Sep 17, 1999
Appl. No.:
09/397439
Inventors:
Michael Chi-Pei Hsing - San Jose CA
Alan Tsu-I Yaung - San Jose CA
Alan Tsu-I Yaung - San Jose CA
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04K 100
US Classification:
380 28, 380 55, 380 51, 380 29, 713182, 713184, 713168, 713202
Abstract:
A technique for password encryption and decryption for user authentication in a federated content management system. One or more commands are executed in a computer to perform a datastore operation on a datastore connected to the computer. A string of characters are received. The string of characters is encrypted based on a first character standard. Then, the encrypted string of characters is transformed to be compatible with a second character standard.
Self-Alignment Technique For Forming Junction Isolation And Wells
US Patent:
5556796, Sep 17, 1996
Filed:
Apr 25, 1995
Appl. No.:
8/428929
Inventors:
Martin E. Garnett - Los Gatos CA
Michael R. Hsing - San Jose CA
Michael R. Hsing - San Jose CA
Assignee:
Micrel, Inc. - San Jose CA
International Classification:
H01L 21265
US Classification:
437 31
Abstract:
A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to define the N-wells. The use of a single masking step to initially define the P+ isolation regions, N+ sinkers, N-wells, and P-wells results in the self-alignment of these regions. Several critical mask alignments are thereby eliminated, thus avoiding/simplifying fabrication steps, conserving die area, and allowing increased component density.
High Voltage Lateral Dmos Device With Enhanced Drift Region
US Patent:
5517046, May 14, 1996
Filed:
Feb 6, 1995
Appl. No.:
8/384168
Inventors:
Michael R. Hsing - San Jose CA
Martin E. Garnett - Los Gatos CA
James C. Moyer - San Jose CA
Martin J. Alter - Los Altos CA
Helmuth R. Litfin - Cupertino CA
Martin E. Garnett - Los Gatos CA
James C. Moyer - San Jose CA
Martin J. Alter - Los Altos CA
Helmuth R. Litfin - Cupertino CA
Assignee:
Micrel, Incorporated - San Jose CA
International Classification:
H01L 2978
US Classification:
257336
Abstract:
A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P. sup. + body contact regions, N. sup. + source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.