DR. MICHAEL TRENT TURNER, M.D.
Osteopathic Medicine at Datapoint Dr, San Antonio, TX

License number
Texas K3654
Category
Osteopathic Medicine
Type
Adult Medicine
License number
Texas K3654
Category
Osteopathic Medicine
Type
Emergency Medicine
Address
Address
8401 Datapoint Dr STE 500, San Antonio, TX 78229
Phone
(210) 614-0180
(210) 615-7170 (Fax)

Personal information

See more information about MICHAEL TRENT TURNER at radaris.com
Name
Address
Phone
Michael Turner, age 70
4820 Garvin Dr, The Colony, TX 75056
Michael Turner
4803 Dove Holw, Texarkana, TX 75501
(903) 880-2423
Michael Turner, age 57
4814 Englewood St, Houston, TX 77026
(713) 444-5129
Michael Turner, age 38
4855 Lazy Timbers Dr, Humble, TX 77346
Michael Turner
4912 Haverwood Ln Apt 334, Dallas, TX 75287
(972) 381-7250

Professional information

Michael Turner Photo 1

Network Engineer At Comal Independent School District

Position:
Network Engineer at Comal Independent School District
Location:
San Antonio, Texas Area
Industry:
Education Management
Work:
Comal Independent School District since Oct 2005 - Network Engineer Hill Country Fabic Recovery Services Nov 1998 - Aug 2005 - Owner
Education:
American Commercial College 1992 - 1994
diploma, Accounting, CAD
Interests:
Scuba Diving, Vinyl Window Decals, AnythingTechnology


Michael Turner Photo 2

Manager, Business Intelligence At Uthscsa

Position:
Manager, Business Intelligence at UTHSCSA
Location:
San Antonio, Texas Area
Industry:
Information Technology and Services
Work:
UTHSCSA - San Antonio, Texas since Jan 2013 - Manager, Business Intelligence University of Texas Health Science Center at San Antonio - San Antonio, TX Jul 2012 - Dec 2012 - Data Architect UT Medicine San Antonio - San Antonio TX Mar 2007 - Jul 2012 - Manager of Decision Support
Education:
Texas A&M University 1987 - 1991
Bachelor of Science (BS), Economics


Michael Turner Photo 3

Michael Turner, San Antonio TX - Teacher

Specialties:
Computer Science
Work:
Hallmark College - San Antonio TX


Michael Turner Photo 4

Michael Turner - San Antonio, TX

Work:
Statewide Appeal
Assistant Manager
H-E-B Grocery - San Antonio, TX
Produce Representative
Education:
Judson High School - Converse, TX
Diploma


Michael Turner Photo 5

Method For Elimination Of Excessive Field Oxide Recess For Thin Si Soi

US Patent:
7037857, May 2, 2006
Filed:
Dec 16, 2003
Appl. No.:
10/737115
Inventors:
Toni D. Van Gompel - Austin TX, US
Mark D. Hall - Austin TX, US
Mohamad Jahanbani - Austin TX, US
Michael D. Turner - San Antonio TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/3205, H01L 21/31
US Classification:
438761, 438585
Abstract:
A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.


Michael Turner Photo 6

Electronic Device Including A Semiconductor Layer And A Sidewall Spacer And A Process Of Forming The Same

US Patent:
2007024, Oct 25, 2007
Filed:
Apr 24, 2006
Appl. No.:
11/409882
Inventors:
Rode Mora - Austin TX, US
Vance Adams - Austin TX, US
Venkat Kolagunta - Austin TX, US
Michael Turner - San Antonio TX, US
Toni Van Gompel - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/336, H01L 27/12
US Classification:
438295000, 257347000
Abstract:
An electronic device can include a substrate, an insulating layer, and a semiconductor layer overlying the insulating layer, wherein the insulating layer lies between the substrate and the semiconductor layer. In one aspect, a process of forming the electronic device can include patterning the semiconductor layer to define an opening extending to the insulating layer. The semiconductor layer has a sidewall and a surface, the surface is spaced apart from the insulating layer, and the sidewall extends from the surface towards the insulating layer. The process can also include forming a sidewall spacer adjacent to the sidewall, wherein the sidewall spacer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the sidewall spacer.


Michael Turner Photo 7

Semiconductor Device Having Trench Isolation For Differential Stress And Method Therefor

US Patent:
7288447, Oct 30, 2007
Filed:
Jan 18, 2005
Appl. No.:
10/977226
Inventors:
Jian Chen - Austin TX, US
Thien T. Nguyen - Austin TX, US
Michael D. Turner - San Antonio TX, US
James E. Vasek - Austin TX, US
International Classification:
H01L 21/64
US Classification:
438165, 257347
Abstract:
A semiconductor device has trenches for defining active regions. After a thin diffusion barrier is deposited in the trenches, some of the trenches are selectively etched to leave different areas in the trench. One of the areas has the diffusion barrier completely removed so that the underlying layer is exposed. Another area has the diffusion barrier remaining. An oxidation step follows so that oxidation occurs at a corner where the diffusion barrier was removed whereas the oxidation is blocked by the diffusion barrier, which functions as a barrier to oxygen. The corners for oxidation are those in which compressive stress is desirable, such as along a portion of the border of a P channel transistor. The corners where the diffusion barrier is left are those in which a compressive stress is undesirable such as the border of an N channel transistor.


Michael Turner Photo 8

Shallow Trench Isolation For Soi Structures Combining Sidewall Spacer And Bottom Liner

US Patent:
2012027, Nov 1, 2012
Filed:
Jul 13, 2012
Appl. No.:
13/548304
Inventors:
Konstantin V. LOIKO - Austin TX, US
Toni D. VAN GOMPEL - Austin TX, US
Rode R. MORA - Austin TX, US
Michael D. TURNER - San Antonio TX, US
Brian A. WINSTEAD - Austin TX, US
Mark D. HALL - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 29/772
US Classification:
257347, 257E29242
Abstract:
A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer () and a dielectric layer () disposed between the substrate and the semiconductor layer, (b) creating a trench () which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure () which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer () which comprises a second material and which is disposed on the bottom of the trench.


Michael Turner Photo 9

Method For Straining A Semiconductor Device

US Patent:
2007029, Dec 27, 2007
Filed:
Jun 26, 2006
Appl. No.:
11/426463
Inventors:
Gregory S. Spencer - Pflugerville TX, US
Stanley M. Filipiak - Pflugerville TX, US
Michael D. Turner - San Antonio TX, US
International Classification:
H01L 21/31, H01L 21/469
US Classification:
438791, 257E21293
Abstract:
A strained semiconductor layer is achieved by an overlying stressed dielectric layer. The stress in the dielectric layer is increased by a radiation anneal. The radiation anneal can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously. The heat is intense, preferably 900-1400 degrees Celcius, but for a very short duration of less than 10 milliseconds; preferably about 1 millisecond or even shorter. The result of the radiation anneal can also be used to activate the source/drain. Thus, this type of radiation anneal can result in a larger change in stress, activation of the source/drain, and still no expansion of the source/drain.


Michael Turner Photo 10

Method Of Improving The Wafer-To-Wafer Thickness Uniformity Of Silicon Nitride Layers

US Patent:
8084088, Dec 27, 2011
Filed:
Jun 30, 2004
Appl. No.:
10/881932
Inventors:
Katja Huy - Dresden, DE
Hartmut Ruelke - Dresden, DE
Michael Turner - San Antonio TX, US
Assignee:
Globalfoundries Inc. - Grand Cayman
International Classification:
C23C 16/00
US Classification:
427255394, 42725528, 42725523
Abstract:
Wafer-to-wafer thickness uniformity may be improved significantly in a process for depositing a silicon nitride layer in that the flow rate of the reactant and the chamber pressure are varied during a deposition cycle. By correspondingly adapting the flow rate and/or the chamber pressure before and after the actual deposition step, the process conditions may be more effectively stabilized, thereby reducing process variations, even after non-deposition phases of the deposition tool, such as a preceding plasma clean process or an idle period of the tool.