MR. MICHAEL T CLARK, RPH
Pharmacy at Congress Ave, Austin, TX
License number
Texas 22549
Category
Pharmacy
Type
Pharmacist
Address
Address
2400 S Congress Ave, Austin, TX 78704
Phone
(512) 442-1578
(512) 444-4255 (Fax)
(512) 444-4255 (Fax)
Personal information
See more information about MICHAEL T CLARK at radaris.comName
Address
Phone
4706 Camargo Ct, College Sta, TX 77845
5006 Edgecliff Dr, Wichita Falls, TX 76302
Professional information
Managing Partner -- Austin Office At Thornton, Biechlin, Segrato, Reynolds &Amp; Guerra, Llc
Position:
Managing Partner -- Austin Office at Thornton, Biechlin, Segrato, Reynolds & Guerra, LLC
Location:
Austin, Texas Area
Industry:
Law Practice
Work:
Thornton, Biechlin, Segrato, Reynolds & Guerra, LLC
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Managing Partner -- Austin Office
Education:
Universit of Texas & Texas Tech School of Law
Method And Apparatus For Controlling Power Management State Transitions Between Devices Connected Via A Clock Forwarded Interface
US Patent:
6446215, Sep 3, 2002
Filed:
Aug 20, 1999
Appl. No.:
09/378026
Inventors:
Derrick R. Meyer - Austin TX
Scott A. White - Austin TX
Michael T. Clark - Austin TX
Philip E. Madrid - Round Rock TX
Scott A. White - Austin TX
Michael T. Clark - Austin TX
Philip E. Madrid - Round Rock TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 126
US Classification:
713310, 713322, 713323, 710262, 710267
Abstract:
A method and apparatus for controlling power management state transitions between two devices, e. g. , a processor and a bus bridge, that are connected through a clock forwarded interface bus in a computer system. The bus bridge is configured to coordinate disconnection of the processor from the interface. Particularly, the bus bridge may use a fist signal to indicate whether or not the processor is to be disconnected from the interface (e. g. a CONNECT signal) and the processor may use a second signal to indicate whether or not the processor is to be disconnected from the interface (e. g. a PROCREADY signal). The processor is disconnected from the interface responsive to both the first signal and the second signal indicating that the processor is to be disconnected. The signals may also be used to reconnect the processor to the interface.
Address Size And Operand Size Prefix Overrides For Default Sizes Defined By An Operating Mode Of A Processor
US Patent:
6571330, May 27, 2003
Filed:
Jan 14, 2000
Appl. No.:
09/483560
Inventors:
Kevin J. McGrath - Los Gatos CA
Michael T. Clark - Austin TX
Michael T. Clark - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 934
US Classification:
712210, 712230, 711208, 711209, 711212, 711214
Abstract:
A processor supports a processing mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, an instruction prefix may be coded into an instruction to override the default address and/or operand size. Thus, an address size of 32 bits may be used when desired, and an operand size of 64 bits may be used when desired.
Processor And Method Implemented By A Processor To Implement Mask Load And Store Instructions
US Patent:
2012011, May 10, 2012
Filed:
Nov 5, 2010
Appl. No.:
12/940591
Inventors:
Kelvin GOVEAS - Austin TX, US
Edward MCLELLAN - Holliston MA, US
Steven BEIGELMACHER - Somerville MA, US
David KROESCHE - Austin TX, US
Michael CLARK - Austin TX, US
Edward MCLELLAN - Holliston MA, US
Steven BEIGELMACHER - Somerville MA, US
David KROESCHE - Austin TX, US
Michael CLARK - Austin TX, US
Assignee:
ADVANCED MICRO DEVICES, INC. - Sunnyvale CA
International Classification:
G06F 9/312, G06F 11/07
US Classification:
714 15, 712225, 714 49, 712E09033, 714E11023, 714E11024
Abstract:
A method of implementing a mask load or mask store instruction by a processor is provided. The method may include receiving the mask load or mask store instruction, a location of a memory operand and a location of corresponding mask bits associated with the memory operand, breaking the received memory operand into a plurality of sub-operands and executing the mask load or mask store instruction on each of the plurality of sub-operands using a fastpath operation or using microcode, wherein the respective mask load or mask store instruction loads or stores each of the plurality of sub-operands based upon the corresponding mask bits.
Processor With Reconfigurable Floating Point Unit
US Patent:
2008020, Aug 28, 2008
Filed:
May 31, 2007
Appl. No.:
11/756166
Inventors:
Ashraf Ahmed - Austin TX, US
Kelvin Domnic Goveas - Austin TX, US
Michael Clark - Austin TX, US
Jelena Ilic - Austin TX, US
Kelvin Domnic Goveas - Austin TX, US
Michael Clark - Austin TX, US
Jelena Ilic - Austin TX, US
Assignee:
ADVANCED MICRO DEVICES, INC. - Sunnyvale CA
International Classification:
G06F 7/38
US Classification:
712222
Abstract:
A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into one or more full-bit operations, when the full-bit mode is indicated, or one or more reduced-bit operations, when the reduced-bit mode is indicated.
Establishing An Operating Mode In A Processor
US Patent:
7124286, Oct 17, 2006
Filed:
Apr 2, 2001
Appl. No.:
09/824890
Inventors:
Kevin J. McGrath - Los Gatos CA, US
Michael T. Clark - Austin TX, US
James B. Keller - Palo Alto CA, US
Michael T. Clark - Austin TX, US
James B. Keller - Palo Alto CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 9/30
US Classification:
712229, 712 43
Abstract:
A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state).
Processor With Power Saving Reconfigurable Floating Point Unit Decoding An Instruction To Single Full Bit Operation Or Multiple Reduced Bit Operations
US Patent:
7565513, Jul 21, 2009
Filed:
Feb 28, 2007
Appl. No.:
11/680331
Inventors:
Ashraf Ahmed - Austin TX, US
Kelvin Domnic Goveas - Austin TX, US
Michael Clark - Austin TX, US
Jelena Ilic - Austin TX, US
Kelvin Domnic Goveas - Austin TX, US
Michael Clark - Austin TX, US
Jelena Ilic - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 9/302
US Classification:
712222, 712209, 713324
Abstract:
A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated.
Data Movement And Initialization Aggregation
US Patent:
7761672, Jul 20, 2010
Filed:
Jun 28, 2007
Appl. No.:
11/770333
Inventors:
Michael T. Clark - Austin TX, US
Matthew Rafacz - Austin TX, US
Matthew Rafacz - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 12/00
US Classification:
711162
Abstract:
A system and method for copying and initializing a block of memory. To copy several data entities from a source region of memory to a destination region of memory, an instruction may copy each data entity one at a time. If an aggregate condition is determined to be satisfied, multiple data entities may be copied simultaneously. The aggregate condition may rely on an aggregate data size, the size of the data entities to be copied, and the alignment of the source and destination addresses.
Multi-Core Integrated Circuit With Shared Debug Port
US Patent:
7665002, Feb 16, 2010
Filed:
Dec 14, 2005
Appl. No.:
11/302942
Inventors:
Scott A. White - Austin TX, US
Michael T. Clark - Austin TX, US
Timothy J. Wood - Austin TX, US
Michael T. Clark - Austin TX, US
Timothy J. Wood - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 31/28
US Classification:
714733, 714727
Abstract:
A single test access port, such as a JTAG-based debug port may be utilized to perform debug operations on logic cores of a multi-core integrated circuit, such as a multi-core processor. The shared debug port may respond to a particular command to enter a debugging mode and may be configured to forward all commands and data to a debugging controller of the integrated circuit during debugging. A mask register may be used to indicate which logic cores of the multi-core integrated circuit should be debugged. Additionally, custom debugging commands may include mask or core select fields to indicate which logic cores should be affected by the particular command. Debugging mode may be initialized for one or more logic cores either externally, such as be asserted a DBREQ signal, or internally, such as by configuring one or more breakpoints.
Sys. Tech At At@T
Position:
Sys. Tech at AT@T
Location:
Austin, Texas Area
Industry:
Telecommunications
Work:
AT@T
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Sys. Tech