Michael Steven Peters
Engineers at Howes St, Fort Collins, CO

6480817, Nov 12, 2002

Sep 1, 1994

08/299395

Michael J. Peters - Fort Collins CO
Richard L. Collins - Fort Collins CO
David M. Musolf - Fort Collins CO
Patrick R. Bashford - Fort Collins CO
Bradley J. Wright - Fort Collins CO

Hynix Semiconductor, Inc. - Seoul

G06F 1750

703 15, 703 13, 703 14, 710305, 716 4, 716 17, 714724

A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library.

6636927, Oct 21, 2003

Sep 24, 1999

09/405345

Michael J. Peters - Fort Collins CO
Donald N. Allingham - Fort Collins CO
Patrick R. Bashford - Fort Collins CO

Adaptec, Inc. - Milpitas CA

G06F 1336

710309, 710306, 710300, 710100, 710305, 710313, 710314

The present invention provides bridge device for transferring data using master-specific prefetch sizes. The bridge device is coupled between a first bus and a second bus with the master devices being coupled to the first bus and the slave devices being coupled to the second bus. The bridge device includes a set of prefetch control registers, a prefetch buffer, and bridge control circuitry. The set of prefetch control registers is arranged to store prefetch sizes of data to be prefetched for a set of the master devices with one prefetch control register being provided for a master device. The prefetch buffer is arranged to store data for transfer. The bridge control circuitry is coupled to the prefetch control registers and the prefetch buffer for transferring data between a source device and a destination device. The bridge control circuitry is further arranged to receive a first data transfer request from a selected master device for transferring data between the selected master device and a selected slave device. The bridge control circuitry issues a second data transfer request to the selected slave device for transferring the data.

6799293, Sep 28, 2004

Jun 19, 2001

09/884270

Michael J. Peters - Fort Collins CO
James R. Klobcar - Winter Springs FL

Adaptec, Inc. - Milpitas CA

G11C 2900

714763, 714 9, 714785, 711111, 370338, 370352

A sparse byte enable indicator for high speed memory access arbitration and a memory controller utilizing same is provided. According to the invention, a sparse byte enable indication is provided to the memory controller with or at about the same time that a request for a write to memory is received from a client. In response to receiving the sparse byte enable indication, the memory controller can begin to initiate a read-modify-write sequence. The present invention allows write operations involving less than complete data words in a first block of data to be completed in fewer clock cycles than in connection with controllers that do not utilize a sparse byte enable indication. The present invention is applicable in connection with any device controlling access to memory in systems utilizing error correction code.

2011023, Sep 29, 2011

Jan 24, 2011

13/012299

Rex Weldon Vedder - Boulder CO, US
Bradford Edwin Golson - Boulder CO, US
Michael Joseph Peters - Fort Collins CO, US

DOT HILL SYSTEMS CORPORATION - Longmont CO

G06F 1/32

713323

A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.

6023748, Feb 8, 2000

Sep 12, 1997

8/928984

Michael J. Peters - Fort Collins CO
Gene Maine - Longmont CO

ADAPTEC, Inc. - Milpitas CA

G06F 1318

711151

A multiple client memory arbitration system to arbitrate client access to a single cache memory in an I/O controller device having at least one internal client in addition to the possibility of at least one external client. The system includes an arbitrator, the ability to determine a configuration type for the I/O controller device selected from a group of configuration types consisting of an unknown device configuration, single device configuration, multiple device master configuration, and multiple device slave configuration, the ability to configure the arbitration device based on a configuration type, the ability to refresh the cache memory independent of the configuration type, and the ability to execute failover control of the cache memory in an event of an I/O controller device failure in a multiple arbitration device configuration.

2002014, Oct 3, 2002

Mar 14, 2002

10/099754

Michael Peters - Fort Collins CO, US
Richard Collins - Fort Collins CO, US
David Musolf - Fort Collins CO, US
Patrick Bashford - Fort Collins CO, US
Bradley Wright - Fort Collins CO, US

G06F017/50

703/014000

A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin. The model provides two modes of operation such that the same model can be used for either chip-level or system-level simulations.

5920490, Jul 6, 1999

Dec 26, 1996

8/773386

Michael J. Peters - Fort Collins CO

Adaptec, Inc. - Milpitas CA

G06F 1750

364578

A logic simulation monitoring system to verify a test stimulus set and generate a test vector set for use on an Automatic Test Equipment (ATE) device during manufacturing tests. The simulation monitor executes unobtrusively as part of the logic simulation to monitor the logic simulation's real time signal activity including contention checks, output strobe margins, and ATE compatibility checks, in addition to extracting the appropriate signal response or vector resulting from a given stimulus. The simulation monitor comprises at least one simulation monitor code block generated from a combination of values from an integrated circuit parameter file and at least one code block template. Output from the simulation monitor includes a report of the contention errors and input signal errors, and a test vector set comprised of the input test stimulus set used with the logic simulation and the stimulus responses resulting from the logic simulation all in an ATE compatible and ready to use format.

6065102, May 16, 2000

Nov 7, 1997

8/965718

Michael J. Peters - Fort Collins CO
Gene Maine - Longmont CO

Adaptec, Inc. - Milpitas CA

G06F 1318

711151

A multiple client memory arbitration system supporting simultaneous arbitration access to a local cache memory and a remote cache memory for mirrored write operations to both the local cache memory and the remote cache memory by one of a local arbitration device or a remote cache memory at a time. The enhanced arbitration system includes active/active failover control by a surviving one of the local arbitration device or the remote arbitration device that have participated in the mirrored write operations between the respective local cache memory and the remote cache memory.

8510598, Aug 13, 2013

Jan 24, 2011

13/012390

Rex Weldon Vedder - Boulder CO, US
Bradford Edwin Golson - Boulder CO, US
Michael Joseph Peters - Fort Collins CO, US

Dot Hill Systems Corporation - Longmont CO

G06F 11/00

714 22, 714 14, 713320

A method for providing reduced power consumption in a computer memory system is provided. The method includes transferring, by a memory controller coupled to a volatile memory, a non-volatile memory, and a buffer, first data from the volatile memory to the buffer. The buffer stores less data than the volatile memory and the non-volatile memory. The method also includes placing the volatile memory into self-refresh mode after transferring the first data to the buffer. The method further includes conveying the first data from the buffer to the non-volatile memory, where the amount of first data exceeds a predetermined threshold. While conveying the first data, the memory controller takes the volatile memory out of self-refresh mode when the amount of first data in the buffer reaches the predetermined threshold. The volatile memory is ready to transfer second data to the buffer when the memory controller is finished transferring the first data.