MICHAEL SHAPIRO, M.D.
Osteopathic Medicine at 34 St, Austin, TX

2008001, Jan 17, 2008

Jul 11, 2006

11/456658

JEAN AUDET - Granby, CA
Louis B. Capps - Georgetown TX, US
Glenn G. Daves - Fishkill NY, US
Anand Haridass - Austin TX, US
Ronald E. Newhart - Essex Junction VT, US
Michael J. Shapiro - Austin TX, US

G01R 27/08, G01R 31/26

324713, 324765

A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.

6221769, Apr 24, 2001

Mar 5, 1999

9/263031

Sang Hoo Dhong - Austin TX
Kevin John Nowka - Round Rock TX
Michael Jay Shapiro - Austin TX

International Business Machines Corporation - Armonk NY

H01L 2144

438667

A method for providing a through wafer connection to an integrated circuit silicon package. A hole is first created in the silicon package with an inner surface area extending from the bottom surface of the silicon package to the top surface of the silicon package. The hole is created by one of two methods. The first involves mechanical drilling with a diamond bit rotated at a high rate of speed. The second involves ultrasonically milling utilizing a slurry and steel fingers. The inner surface area of the hole is covered with an insulating material to insulate the conductive material which is later deposited and to serve as a diffusion barrier, then a seed material is placed in the hole. Finally, the hole is filled with a conductive material which is utilized to provide large power inputs or signaling connections to the integrated circuit chips.

8495636, Jul 23, 2013

Dec 19, 2007

11/959906

Michael A. Paolini - Austin TX, US
Michael Jay Shapiro - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/46

718102, 718 1, 718100, 718107

A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.

2013011, May 9, 2013

Nov 4, 2011

13/289071

MICHAEL J. SHAPIRO - AUSTIN TX, US
GARY D. CARPENTER - AUSTIN TX, US
ALAN J. DRAKE - AUSTIN TX, US
RACHEL GORDIN - HAIFA, IL
EDMUND J. SPROGIS - UNDERHILL VT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

G05F 1/10, H01L 21/02, H01F 5/00, H01L 27/06

323282, 257531, 438381, 336200, 257E27018, 257E21022

A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

8327126, Dec 4, 2012

Aug 25, 2008

12/197357

Thomas Edward Cook - Essex Junction VT, US
Glenn G. Daves - Fishkill NY, US
Ronald Edward Newhart - Essex Junction VT, US
Michael A. Paolini - Austin TX, US
Michael Jay Shapiro - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/00, G06F 9/22, G06F 9/24, G06F 9/46

713100, 713 1, 712 15, 718100, 718102, 718104, 718105

A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

8614512, Dec 24, 2013

Sep 14, 2012

13/615804

Luc Guerin - Granby, CA
Mario J. Interrante - New Paltz NY, US
Michael J. Shapiro - Austin TX, US
Thuy Tran-Quinn - Katonah NY, US
Van T. Truong - Brossard, CA

International Business Machines Corporation - Armonk NY

H01L 29/40

257779, 257738, 257780, 257781, 257E23026

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

8312455, Nov 13, 2012

Dec 19, 2007

11/960021

Michael A. Paolini - Austin TX, US
Michael Jay Shapiro - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 9/46

718100, 712 30, 712220

A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.

7870337, Jan 11, 2011

Nov 28, 2007

11/946249

Thomas E. Cook - Essex Junction VT, US
Michael J. Shapiro - Austin TX, US
Naresh Nayar - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 13/00, G06F 13/28, G01R 21/00, G01R 21/06, G01R 19/00

711118, 711154, 711E12041, 702 60, 702 64

A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e. g. , at cores, cache memories, memory controller, etc. ) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.

8631706, Jan 21, 2014

Jul 21, 2010

12/840861

Nickolaus J Gruendler - Manor TX, US
Paul M Harvey - Austin TX, US
Tae Hong Kim - Round Rock TX, US
Sang Y Lee - Austin TX, US
Michael J Shapiro - Austin TX, US

International Business Machines Corporation - Armonk NY

G01L 9/12, H01R 9/00, H05K 7/20

73718, 73724, 361718, 361773

One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.

2008012, May 29, 2008

Sep 1, 2006

11/469550

Louis B. Capps - Georgetown TX, US
Ronald E. Newhart - Essex Junction VT, US
Michael J. Shapiro - Austin TX, US

G06F 9/318, G06F 15/76

712 30, 712E09035

A method, apparatus, and computer program product for using a multi-core integrated circuit to extend the reliability or operating life of an electronic device.