MICHAEL R SMITH, NP-C
Nursing at Idaho St, Boise, ID
License number
Idaho NP-1084A
Category
Nursing
Type
Family
Address
Address
125 E Idaho St STE 203, Boise, ID 83712
Phone
(208) 338-0148
(208) 336-4027 (Fax)
(208) 336-4027 (Fax)
Personal information
See more information about MICHAEL R SMITH at radaris.comName
Address
Phone
401 Elk Creek Rd, Idaho City, ID 83631
Professional information
Michael Smith
Location:
Boise, Idaho Area
Industry:
Information Technology and Services
Skills:
Project Management
Trench Corner Effect Bidirectional Flash Memory Cell
US Patent:
2005025, Nov 24, 2005
Filed:
Jul 25, 2005
Appl. No.:
11/188891
Inventors:
Michael Smith - Boise ID, US
International Classification:
H01L029/788
US Classification:
257329000
Abstract:
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The trench is filled with an oxide dielectric material and a control gate is formed over the oxide-filled trench. Source/drain regions are adjacent the trench sides with the trapping material. An energy barrier between the drain and source regions has two local high points that correspond to the trench corners. To read the device, sufficient gate voltage is applied to invert the channel and a sufficient drain voltage is applied to pull down the drain-side barrier. If charges of opposite polarity are trapped in the source-side trench corner, the source barrier will be significantly lowered so that current flows between source and drain under read conditions.
Trench Corner Effect Bidirectional Flash Memory Cell
US Patent:
2005025, Nov 17, 2005
Filed:
Jul 25, 2005
Appl. No.:
11/188497
Inventors:
Michael Smith - Boise ID, US
International Classification:
H01L021/335
US Classification:
438142000
Abstract:
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being lined with a trapping material. The trench is filled with an oxide dielectric material and a control gate is formed over the oxide-filled trench. Source/drain regions are adjacent the trench sides with the trapping material. An energy barrier between the drain and source regions has two local high points that correspond to the trench corners. To read the device, sufficient gate voltage is applied to invert the channel and a sufficient drain voltage is applied to pull down the drain-side barrier. If charges of opposite polarity are trapped in the source-side trench corner, the source barrier will be significantly lowered so that current flows between source and drain under read conditions.
Using Icons To Represent Physical Keys In Navigation Aids
US Patent:
2002017, Nov 21, 2002
Filed:
May 16, 2001
Appl. No.:
09/860182
Inventors:
Eric Christianson - Meridian ID, US
Rhonda Grindstaff - Boise ID, US
Michael Smith - Boise ID, US
Rhonda Grindstaff - Boise ID, US
Michael Smith - Boise ID, US
International Classification:
G06F003/14
US Classification:
345/835000
Abstract:
The use of icons to represent the physical keys of a device such as a facsimile machine, copier, scanner, printer, and the like, displayed as visual cues to enhance the user-friendliness of such a device. Icons corresponding to active physical keys of the device are displayed on a display to visually inform a user of the device operations available to the user. Only those icons corresponding to active physical keys are displayed.
Isolation Trench Structure
US Patent:
2009027, Nov 12, 2009
Filed:
May 8, 2008
Appl. No.:
12/117391
Inventors:
Michael A. Smith - Boise ID, US
Xiaolong Fang - Boise ID, US
Xiaolong Fang - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 23/58
US Classification:
257513, 257E23002
Abstract:
Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench structure. One such isolation trench structure includes a first isolation trench portion associated with a surface of the substrate and having a first pair of opposing sidewalls that are each substantially perpendicular to the surface of the substrate. A second isolation trench portion includes a second pair of sidewalls within the substrate that are each angled obliquely with respect to the surface of the substrate, where the second isolation trench portion has a separation between the second pair of sidewalls that decreases as a distance from the first isolation trench portion increases. A third isolation trench portion includes a third pair of sidewalls within the substrate that are each substantially perpendicular to the surface of the substrate.
Semiconductor Constructions
US Patent:
2010027, Nov 4, 2010
Filed:
Jul 15, 2010
Appl. No.:
12/837378
Inventors:
Michael A. Smith - Boise ID, US
Sukesh Sandhu - Boise ID, US
Xianfeng Zhou - Meridian ID, US
Graham Wolstenholme - Boise ID, US
Sukesh Sandhu - Boise ID, US
Xianfeng Zhou - Meridian ID, US
Graham Wolstenholme - Boise ID, US
International Classification:
H01L 29/06
US Classification:
257510, 257368, 257E2902
Abstract:
The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H, with the Hbeing present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.
Apparatus With Capacitive Coupling And Associated Methods
US Patent:
2012003, Feb 16, 2012
Filed:
Aug 16, 2010
Appl. No.:
12/857277
Inventors:
Michael Smith - Boise ID, US
International Classification:
H01L 29/78, H01L 21/326
US Classification:
257336, 438468, 257E29256, 257E21327
Abstract:
Transistors are described, along with methods and systems that include them. In one such transistor, a field plate is capacitively coupled between a first terminal and a second terminal. A potential in the field plate modulates dopant in a diffusion region in a semiconductor material of the transistor. Additional embodiments are also described.
Structure And Method Of Fabricating A Transistor Having A Trench Gate
US Patent:
2005012, Jun 9, 2005
Filed:
Jan 20, 2005
Appl. No.:
11/038985
Inventors:
Michael Smith - Boise ID, US
Mark Helm - Boise ID, US
Kirk Prall - Boise ID, US
Mark Helm - Boise ID, US
Kirk Prall - Boise ID, US
International Classification:
H01L021/8242, H01L021/336, H01L021/76
US Classification:
438270000, 438294000
Abstract:
An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.
Nand Flash Peripheral Circuitry Field Plate
US Patent:
2009021, Sep 3, 2009
Filed:
Feb 29, 2008
Appl. No.:
12/040424
Inventors:
Michael A. Smith - Boise ID, US
International Classification:
H01L 21/336, H01L 29/78
US Classification:
257409, 438289, 257E21409, 257E29266
Abstract:
A high voltage device for use in periphery circuitry of a NAND flash memory device comprising a field plate.
Michael Smith
Location:
Boise, Idaho Area
Industry:
Management Consulting