MICHAEL LYNN NIX, M.D.
Medical Practice at 12 St, Austin, TX

4926363, May 15, 1990

Sep 30, 1988

7/251309

Michael A. Nix - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1100

364579

A modular test structure for performing testing on a single chip having a plurality of different functional blocks is provided which includes test interface logic circuitry (24) formed on each of the functional blocks (16-22) so that each block can be operated as a self-contained module. Test generation logic circuitry (40) is formed in a bus interface unit (12) and is used to select one or more of the functional blocks (16-22) for testing and for placing the selected functional blocks (16-22) in a test mode. The test interface logic circuitry (24) on the selected functional blocks under test sends data direction information to the bus interface unit (12) to indicate how individual bits of a data bus are to be used for inputs and outputs during testing.

2013017, Jul 4, 2013

Dec 29, 2011

13/339444

Anil Kumar - Clifton Park NY, US
Michael A. Nix - Austin TX, US
Moises E. Robinson - Austin TX, US
Carlin D. Cabler - Austin TX, US

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

H02H 7/20

361 19

A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

4862409, Aug 29, 1989

Jun 13, 1988

7/205636

Michael A. Nix - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 900

364900

An asynchronous interrupt status bit circuit for use in conjunction with a microprocessor, which guarantees that no interrupting conditions are missed and that no single interrupting condition is indicated twice, includes a master latch (12), a transfer gate (14), a clocked latch (16), an inverter (18), an output driver circuit (20), and a clearing circuit (22, 24). The master latch (12) is responsive to an interrupt input signal for generating an interrupting logic signal at its output which is latched to a low logic level. The clearing circuit (22, 24) is responsive to a control signal for generating a clear signal to clear the output of the master latch (12) to a high level only when the control signal is latched at a high level before the time a true read signal is making a high-to-low transition. The next read signal causes an output signal having a low level to be read by the microprocessor if no interrupt input signal has occurred.

7978118, Jul 12, 2011

Feb 1, 2010

12/697789

Ahmed Abdell-Ra'oof Younis - San Antonio TX, US
Michael A. Nix - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H03M 1/34

341163, 341155

A 1. 5-bit algorithmic analog-to-digital converter (ADC) generates a digital value representative of an input voltage. The ADC implements a series of conversion cycles for a conversion operation. Each conversion cycle has three sub-cycles: a scaling sub-cycle, a first sample sub-cycle, and a second sample sub-cycle. In the scaling sub-cycle, the residual voltage from the previous conversion cycle is doubled to generate a first voltage. In the first sample sub-cycle, a first bit of a corresponding bit pair is determined based on the polarity of the first voltage. The first voltage is either increased or decreased by a reference voltage based on the polarity of the first voltage to generate a second voltage. In the second sample sub-cycle, a second bit of the corresponding bit pair is determined based on the polarity of the second voltage. The second voltage then is either increased or decreased by the reference voltage based on the polarity of the second voltage to generate the residual voltage used for the next conversion cycle in the series.

7436216, Oct 14, 2008

Jun 14, 2006

11/452858

Brian T. Brunn - Austin TX, US
Michael A. Nix - Austin TX, US
Ahmed Younis - Austin TX, US

Xilinx, Inc. - San Jose CA

H03F 3/45

326 83, 330260, 330 69, 327108

A method and apparatus for combining an alternating current (AC) coupling technique with a low frequency restoration technique to provide AC coupling with low frequency restoration of the attenuated low frequency content. The low frequency restoration circuit operates to extract low frequency information prior to being high-pass filtered by the AC coupling circuit. The low frequency restoration circuit then buffers the low frequency information through a low frequency restoration amplifier, applies a programmable common mode voltage to the buffered, low frequency information, and then restores the buffered, common mode adjusted, low frequency information to the output of the AC coupling circuit.

5299144, Mar 29, 1994

Jun 17, 1992

7/900000

John G. Bartkowiak - Austin TX
Michael A. Nix - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 738, G06F 15336

36471501

The present invention provides an apparatus and method for generating a covariance matrix. According to one aspect of the invention, an apparatus is provided which generally includes a memory, a circular buffer, a multiply-accumulator, and an arithmetic logic unit. The memory contains an array of values representative of a plurality of samples, and the circular buffer is configured to provide a predetermined number of memory locations. A method for generating the covariance matrix is further provided which uses the architecture listed above to efficiently generate a covariance matrix based on the values in the memory. In one aspect of the invention, the method provides that the memory, the circular buffer, the multiply-accumulator, and the arithmetic logic unit, all operate in parallel to fully exploit the resources provided by the architecture.

8410833, Apr 2, 2013

Mar 30, 2011

13/076071

Michael A. Nix - Austin TX, US
Golam R. Chowdhury - Austin TX, US
Curtis M. Brody - Austin TX, US
Faisal A. Syed - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

H03L 7/00

327143, 327198

A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.