MICHAEL LESTER WISE
Pilots at Walsh Rd, La Grange, NY

6596580, Jul 22, 2003

Oct 18, 2001

09/982574

Jingyu Lian - Walkkill NY
Greg Costrini - Hopewell Junction NY
Laertis Economikos - Wappingers Falls NY
Michael Wise - Lagrangeville NY

Infineon Technologies AG
International Business Machines Corporation - Armonk NY

H01L 218242

438253, 438 3, 438396, 257303, 257306, 257310

The exposure of the interface between the bottom electrode and barrier layer to a high temperature oxygen ambience is avoided by recessed Pt-in-situ deposited with a barrier layer.

6794705, Sep 21, 2004

Dec 28, 2000

09/751551

Jingyu Lian - Wallkill NY
Chenting Lin - Poughkeepsie NY
Nicolas Nagel - Yokohama, JP
Michael Wise - Lagrangeville NY

Infineon Technologies AG - Munich

H01L 27108

257310, 257295, 257296, 257303, 257304, 257311, 257906, 257908

A multi-layer electrode ( ) and method of fabrication thereof in which a conductive region ( ) is separated from a barrier layer ( ) by a first conductive liner ( ) and a second conductive liner ( ). First conductive layer ( ) comprises Pt, and second conductive liner ( ) comprises a thin layer of conductive oxide. The multi-layer electrode ( ) prevents oxygen diffusion through the top conductive region ( ) and reduces material variation during electrode patterning.

2004019, Oct 7, 2004

Apr 7, 2003

10/408339

Jingyu Lian - Wallkill NY, US
Kwong Wong - Wappingers Falls NY, US
Michael Wise - Lagrangeville NY, US
Young Limb - Poughkeepsie NY, US
Nicolas Nagel - Yokohama, JP

B32B009/04, B32B015/04

428/446000, 428/450000, 427/058000

Si, Al, Al plus TiN, and Ir02 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (5i0) substrate in capacitor structures of memory devices.

6812092, Nov 2, 2004

Dec 19, 2000

09/740113

Mihel Seitz - Radebeul, DE
Michael Wise - Lagrangeville NY
Christian Dubuc - St-Hyacinthe, CA

Infineon Technologies - Munich

H01L 218242

438243, 438197, 438239, 438268, 438279

A Dynamic Random Access Memory is fabricated in a semiconductor body of a first conductivity type in which there have been formed an array of memory cells which each include a trench capacitor and a vertical Insulated Gate Field Effect Transistor (IGFET). Each IGFET includes first and second output regions of a second opposite conductivity type and a gate which is separated from a surface of the semiconductor body by a gate dielectric layer. A gate electrode connected to the gate is formed using a Damascene process with insulating sidewall spacer regions being formed before the gate electrode is formed. Borderless contacts, which are self aligned, are made to the first output regions of each transistor using a Damascene process.

6420216, Jul 16, 2002

Mar 14, 2000

09/525729

Larry Clevenger - LaGrangeville NY
Louis L. C. Hsu - Fishkill NY
Chandrasekhar Narayan - Hopewell Junction NY
Jeremy K. Stephens - New Windsor NY
Michael Wise - LaGrangeville NY

International Business Machines Corporation - Armonk NY
Infineon Technologies North America Corp. - San Jose CA

H01L 2182

438132, 438333

An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride.

6437401, Aug 20, 2002

Apr 3, 2001

09/824957

Jack A. Mandelman - Stormville NY
Stephan Kudelka - Fishkill NY
Andreas Knorr - Fishkill NY
Stephen Rahn - LaGrangeville NY
Helmut Tews - Poughkeepsie NY
Michael Wise - Lagrangeville NY

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

H01L 2976

257330, 257331, 257328

A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

6821865, Nov 23, 2004

Dec 30, 2002

10/248233

Michael Wise - Lagrangeville NY
Andreas Knorr - Austin TX

Infineon Technologies AG - Munich

H01L 21762

438435, 438697, 257E21546

A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.

7319270, Jan 15, 2008

Aug 30, 2004

10/929157

Jingyu Lian - Wallkill NY, US
Chenting Lin - Poughkeepsie NY, US
Nicolas Nagel - Yokohama, JP
Michael Wise - Lagrangeville NY, US

Infineon Technologies AG - Munich

H01L 23/48, H01L 23/52, H01L 29/40, H01L 27/10, H01L 29/74

257758, 257207, 257208, 257211, 257700, 257750, 257751, 257759, 257760, 257761, 257769, 257774

An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.

7091103, Aug 15, 2006

Dec 9, 2002

10/314865

Jochen Beintner - Wappingers Falls NY, US
Laertis Economikos - Wappingers Falls NY, US
Michael Wise - Lagrangeville NY, US
Andreas Knorr - Austin TX, US

International Business Machines Corporation - Armonk NY
Infineon Technologies North America Corporation - San Jose CA

H01L 21/76, H01L 21/461, H01L 21/302

438424, 438427, 438690, 438691

CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.