Michael L Anderson
Accountancy at Cascade, Colorado Springs, CO

6122336, Sep 19, 2000

Sep 11, 1997

8/927947

Michael B. Anderson - Colorado Springs CO

LSI Logic Corporation - Milpitas CA

H04L 2540, H04L 700, H03D 324

375371

The present invention provides a digital clock recovery circuit, which includes a frequency synthesizer generating a number of clock phase signals. The digital clock recovery circuit also includes a phase interpolation unit, which interpolates the clock phase signals from the frequency synthesizer to increase the number of clock phase signals. Additionally, the digital clock recovery circuit also includes a phase detector, a digital filter, and a phase selection unit. The phase detector has an output connected to a digital filter, which is connected to the phase selection unit. The phase detector sends signals filtered through the digital filter to select clock phase signals input into the phase selection unit from the phase interpolation unit. The output of the phase selector provides the recovered clock signal and also connected to the input phase detector.

8508211, Aug 13, 2013

Nov 12, 2009

12/616996

Michael Brian Anderson - Colorado Springs CO, US

Linear Technology Corporation - Milpitas CA

H01L 35/00, G05F 1/10, G05F 3/16

323313, 327513, 327539

Method and system for developing low noise bandgap references. A stacked ΔVgenerator is disclosed for generating ΔV. The stacked ΔVgenerator includes an error amplifier configured to generate an output based on an error signal provided by a first stack of the ΔVgenerator. The first stack of the ΔVis coupled to a first sub-circuit and the error amplifier to form a closed loop. The first sub-circuit is coupled to a power supply and ground and configured to provide a source current between the power supply and the ground. The stacked ΔVgenerator also includes a second sub-circuit coupled to the output of the error amplifier, the first and second stacks, and the ground, as well as a second stack of the ΔVgenerator, which is coupled to the first stack and the second sub-circuit. The ΔVis measured at outputs of the first and second stacks and equals the sum of individual ΔVs of the first and second stacks.

5864246, Jan 26, 1999

Mar 31, 1997

8/828496

Michael B. Anderson - Colorado Springs CO

LSI Logic Corporation - Milpitas CA

H03B 1900

327122

A circuit for multiplying a clock signal. The circuit includes a phase interpolator having two inputs for receiving complementary clock signals. The output of the phase interpolator is connected to an input in an exclusive OR gate. One of the two complementary input signals also is sent into the exclusive OR gate, wherein a multiplied clock signal is generated at the output of the exclusive OR gate.

6246278, Jun 12, 2001

Dec 22, 1995

8/580036

Michael B. Anderson - Colorado Springs CO
Kenneth C. Schmitt - Colorado Springs CO
David M. Weber - Monument CO

LSI Logic Corporation - Milpitas CA

G06F 104

327295

A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

5477198, Dec 19, 1995

Jun 23, 1994

8/264863

Michael B. Anderson - Colorado Springs CO
Frank Gasparik - Monument CO

AT&T Global Information Solutions Company - Dayton OH
Hyundai Electronics America - Milpitas CA

H03B 500

331177R

A circuit design extending the range and linearizing the transfer characteristic of a fast voltage controlled oscillator (VCO). In addition, a multi-range VCO is described. Range extension is achieved by modifying the delay cell of a current controlled ring oscillator. The VCO transfer characteristic is linearized by piece-wise linear current control added to the delay cell. Additionally, a VCO capable of multi-range operation is provided. With the addition of multiple current sources which control booster inverter current, and by selectively enabling the additional current sources, a VCO with multiple frequency ranges can be achieved.

6243784, Jun 5, 2001

Oct 22, 1999

9/425493

Michael B. Anderson - Colorado Springs CO
Gregory A. Tabor - Colorado Springs CO
Mark J. Jander - Colorado Springs CO

LSI Logic Corporation - Milpitas CA

H03H 1126

710129

A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

7420359, Sep 2, 2008

Mar 17, 2006

11/377451

Michael B. Anderson - Colorado Springs CO, US
Andrew J. Gardner - Colorado Springs CO, US
Robert Chiacchia - Colorado Springs CO, US

Linear Technology Corporation - Milpitas CA

G05F 3/16, G05F 1/10

323316, 323281, 327535, 327538

A bandgap voltage reference circuit having temperature curvature correction, comprises a bandgap voltage source configured to generate an output voltage, and a novel curvature correction circuit. The correction circuit is responsive to the bandgap voltage source output voltage and connected to apply a curvature correction signal to the bandgap voltage source to compensate for output voltage temperature dependency of the bandgap voltage source.