Michael John Erickson
Engineers at Empire Ave, Loveland, CO

6487624, Nov 26, 2002

Aug 13, 1999

09/374051

Michael John Erickson - Loveland CO
Daniel V. Zilavy - Ft. Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1300

710302, 710 58, 710330, 307 64, 307141

A method and apparatus for hot swapping and bus extension without data corruption. During the hot swapping of a circuit board in a bus, the bus is extended onto or retracted from the circuit board in a manner which does not corrupt the data on the bus. The extension or retraction of the bus is detected and a bus reset is asserted interrupting and preventing transactions on the bus. The bus reset is asserted for a minimum amount of time to allow the bus to stabilize after the hot swap. A bus extension/retraction detection component and a bus reset component perform these functions.

6408343, Jun 18, 2002

Mar 29, 1999

09/274385

Michael J. Erickson - Loveland CO
Daniel V. Zilavy - Ft. Collins CO
Glenn W. Strunk - Ft. Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1314

710 15, 710 18, 714 11, 714 25, 714 40, 714 44

A device and method for a peripheral adapter of a dual SCSI bus enclosure is described. An adapter can operate alone or in pairs to provide different modes of operation, including simplex, duplex, and cluster. When used in pairs, two adapters interconnect internally to the enclosure through internal cross-coupling bus repeaters that can be selectively enabled or disabled. The adapters are hot-swappable and have the ability to automatically self configure. In the cluster mode, the adapter supports failover capability from a master adapter to a redundant adapter.

6378084, Apr 23, 2002

Mar 29, 1999

09/277219

Glenn W. Strunk - Ft. Collins CO
Michael J. Erickson - Loveland CO
Daniel V. Zilavy - Ft. Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1100

714 2, 711112

A device and method for enclosure processing of a dual SCSI bus enclosure is described. A single SCSI enclosure processor is provided on an adapter that can operate alone or in pairs to provide different modes of operation, including simplex, duplex, and cluster. When used in pairs, two adapters interconnect internally to the enclosure through internal cross-coupling bus repeaters. The adapters have the ability to automatically configure themselves. In the cluster mode, a first enclosure processor on a first adapter assumes an active status, while a second enclosure processor on a second adapter waits in a standby mode. The standby enclosure processor detects when the active enclosure processor has failed, misoperated, or been removed and automatically failsover, assuming the identity of the active enclosure processor, without disruption to the system. Hot-swapping of the adapter boards is therefore possible.

6898775, May 24, 2005

Aug 7, 2003

10/636903

Michael John Erickson - Loveland CO, US
Paul J. Mantey - Fort Collins CO, US
John S Atkinson - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F017/50

716 15, 716 16, 716 17

The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.

6915441, Jul 5, 2005

Jul 30, 2001

09/917984

David R. Macior wski - Road Parker CO, US
Michael John Erickson - Loveland CO, US
Paul J. Mantey - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F001/28

713340, 713300

A system for providing basic system control functions upon failure of all management processors in a computer system. During normal system operation, a plurality of management processors monitor system sensors that detect system power, temperature, and cooling fan status, and make necessary adjustments. Each management processor normally provides an output signal indicating that it is operating property. A high-availability controller monitors each of these signals to verify that there is at least one operating management processor. When none of the processors indicate that they are operating properly, the high-availability controller monitors the system sensors and updates system indicators. If a problem develops, such as failure of a power supply or a potentially dangerous increase in temperature, the high-availability controller sequentially powers down the appropriate equipment to protect the system from damage.

2004022, Nov 11, 2004

Jul 30, 2001

09/918024

Michael Erickson - Loveland CO, US
David MacIorowski - Parker CO, US
Paul Mantey - Ft. Collins CO, US

G06F013/00, G06F013/38

710/200000

A bus bridge is capable of transferring information between a first serial bus and a target serial bus. The bridge is capable of operating as a bus slave on the first serial bus, and as a bus master on the target serial bus. The first serial bus in a particular embodiment is an IIC serial bus, while the target serial bus is a JTAG bus. There may be additional target serial busses, and there is a selection apparatus whereby commands may be directed to a particular target serial bus.

6914951, Jul 5, 2005

Jul 24, 2001

09/912191

Michael John Erickson - Loveland CO, US
Bradley D. Winick - Fort Collins CO, US
David R. Maciorowski - Parker CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

H04B001/10

375350, 375360, 327 34

Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.

7089413, Aug 8, 2006

Mar 5, 2003

10/382346

Michael John Erickson - Loveland CO, US
David L. Tharp - Fort Collins CO, US
Daniel V. Zilavy - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 15/177

713 2, 713 1

Techniques are disclosed for resetting agents in a computer system without requiring the computer system, or partitions thereof, to be reset. In one embodiment, each agent in the system is associated with a corresponding partition. A reset signal directed to an agent is redirected to a reset type selector which determines whether the partition associated with the agent is in a run state (an “unsafe run state”) in which resetting the agent will cause the partition to crash. If the partition is in an unsafe run state, a soft reset is performed on the agent. Otherwise, a hard reset is performed on the agent. If performing a soft reset does not solve the problem that was the impetus for the reset signal, the partition may be brought into a safe run state before performing a hard reset on it.

6954929, Oct 11, 2005

Jul 30, 2001

09/917982

Michael John Erickson - Loveland CO, US
David R. Maciorowski - Parker CO, US
Christopher S Kroeger - Longmont CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F009/44

717173, 717170, 710220

The invention provides a method of implementing firmware updates to programmable parts within circuit boards on a manufacturing line. An image file of firmware for each of the parts is created and stored on a firmware server. The programmable parts are preferably integrated with the printed circuit boards; each of the boards networks to the firmware server by connection with an interface server, such that the image files download to the circuit board for programming the board's internal programmable parts. Networking between the parts and the firmware server can include communications across the Internet and/or one or more area networks. Multiple interface servers may be integral with the products incorporating the programmable parts so that many products may be updated concurrently.

7746883, Jun 29, 2010

Mar 1, 2005

11/069073

Michael J. Erickson - Loveland CO, US
Daniel V. Zilavy - Fort Collins CO, US
Edward A. Cross - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

H04J 3/16, H04J 3/22, H04L 12/66, G06F 15/16

370419, 370463, 370466, 370469, 709250

Systems, methodologies, media, computing devices, network adapters, and other embodiments associated with network communications are described. One exemplary system embodiment includes a multi-drop Ethernet network.