MICHAEL JOHN CRAREN
Pilots at Juniper Rd, Holliston, MA

6665755, Dec 16, 2003

Dec 22, 2000

09/742286

Richard P. Modelski - Hollis NH
Michael J. Craren - Holliston MA
Adrian M. Kristiansen - Somerville MA

Nortel Networks Limited

G06F 1300

710100, 711154, 712205

External memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The route switch packet architecture includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

6633880, Oct 14, 2003

Dec 22, 2000

09/741859

Richard P. Modelski - Hollis NH
Michael J. Craren - Holliston MA
Adrian M. Kristiansen - Somerville MA
Richard L. Angle - Wellesley MA
Geoff B. Ladwig - Chelmsford MA

Nortel Networks Limited

G06F 1730

707100, 707 3

A method performs a radix search data structure. The method receives a key containing a set of data bits. The method determines a reference index based on a first subset of data bits in the key. The method indexes a reference table based on the reference index to locate a reference field. The method determines a result index based on a second subset of data bits in the key and the reference field. The method then indexes a result table based on the result index to locate a result of a radix search data structure.

6981077, Dec 27, 2005

Dec 22, 2000

09/741846

Richard P. Modelski - Hollis NH, US
Michael J. Craren - Holliston MA, US

Nortel Networks Limited

G06F013/00, G06F012/00

710100, 711154, 712205

Global access bus architecture includes a master request bus and a slave request bus separated from each other and pipelined. The global access bus architecture includes packet input global access bus software code for flow of data packet information from a flexible input data buffer to an analysis machine, packet data global access bus software code for flow of packet data between a flexible data input bus and a packet manipulator, statistics data global access bus software code for connection of an analysis machine to a packet manipulator, private data global access bus software code for connection of an analysis machine to an internal memory engine, lookup global access bus software code for connection of an analysis machine to an internal memory engine, results global access bus software code for providing flexible access to an external memory, and results global access bus software code for providing flexible access to an external memory.

7039627, May 2, 2006

Dec 22, 2000

09/742290

Richard P. Modelski - Hollis NH, US
Michael J. Craren - Holliston MA, US
Adrian M. Kristiansen - Somerville MA, US
Richard L. Angle - Wellesley MA, US
Geoff B. Ladwig - Chelmsford MA, US

Nortel Networks Limited

G06F 17/30

707 2, 707 3, 707102

A method performs a radix search data structure. The method selects a reference table based on a value of a selectable parameter. The reference table includes at least one of a valid reference table and a transition reference table, and contains a set of data bits. The method receives a key containing a set of data bits. The method indexes the reference table using at least a subset of data bits in the key. The method determines a result index based on at least a subset of data bits in the reference table. The method then indexes a result table based on the result index to reference a result of a radix search data structure.

2002008, Jun 27, 2002

Dec 22, 2000

09/741857

Richard Modelski - Hollis NH, US
Michael Craren - Holliston MA, US

G06F015/00, G06F015/76, G06F007/38

712/018000, 712/225000

A multi-thread packet processor which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

7283747, Oct 16, 2007

Aug 15, 2001

09/931643

Bruce A. Schofield - Tyngsboro MA, US
James V. Luciani - Acton MA, US
Michael J. Craren - Holliston MA, US

Nortel Networks Limited

H04J 14/00

398 57, 398 51

An optical switch router performs both optical switching and traditional routing. The optical switch router includes optical interfaces for coupling to one or more incoming optical fibers and to one or more outgoing optical fibers, and also includes a number of traditional router ports. Individual incoming optical data streams received over the incoming optical fiber(s) can be selectively passed through to one or more of the outgoing optical fibers or “dropped” from the optical communication path for traditional routing. Routed traffic, which can be received over the router ports or from the “dropped” optical data streams, can be forwarded over optical data streams that are “added” to the outgoing optical fiber(s). The “added” optical data streams may be added to the outgoing optical fiber(s) at any unused wavelengths, including, but not limited to, the wavelengths of the “dropped” optical data streams.

7369554, May 6, 2008

Dec 22, 2000

09/741856

Richard P. Modelski - Hollis NH, US
Adrian M. Kristiansen - Somerville MA, US
Michael J. Craren - Holliston MA, US

Nortel Networks Limited

H04L 12/28

370392, 370389, 709224

A method performs a plurality of filter operations on a data packet using an instruction. The method receives an instruction to filter at least one data packet. The method retrieves a filter result based on the received instruction. The method then performs a plurality of filter operations on the at least one data packet in accordance with the retrieved filter result.

6934780, Aug 23, 2005

Oct 3, 2003

10/678677

Richard P. Modelski - Hollis NH, US
Michael J. Craren - Holliston MA, US
Adrian M. Kristiansen - Somerville MA, US

Nortel Networks Limited

G06F013/00, G06F012/00

710100, 711711, 711154, 711712, 711205

An external memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator.

7013302, Mar 14, 2006

Dec 22, 2000

09/741999

Richard P. Modelski - Hollis NH, US
Michael J. Craren - Holliston MA, US

Nortel Networks Limited

G06F 17/30

707 10, 707 1, 7071041, 709228

A bit field direct manipulation device which processes data packets using a multi-threaded pipelined machine, wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.

2012027, Nov 1, 2012

Jul 11, 2012

13/546144

Nicolas Tausanovitch - Windham NH, US
Michael Craren - Holliston MA, US
Hamid Assarpour - Arlington MA, US

ROCKSTAR BIDCO, LP - New York NY

H04L 12/24, H04L 12/26

370216, 3702411

In an Ethernet network element comprising at least one line interface element and a central processing unit (CPU) to control forwarding of data packets at the network element, a method comprising receiving continuity check messages (CCMs) at the at least one line interface element, and processing the CCMs in the at least one line interface element to provide continuity checks for connections to the network element without requiring processing of CCMs by the CPU.