Michael Gwynn Wilson
Security Companies and Guards in Salt Lake City, UT

5598154, Jan 28, 1997

Dec 2, 1994

8/348669

Michael L. Wilson - Salt Lake City UT
John W. Zscheile - West-Farmington UT
Richard J. Saggio - Salt Lake City UT
Alan E. Lundquist - Salt Lake City UT

Unisys Corporation - Blue Bell PA

H03M 700

341 50

A set of independent pseudonoise (PN) component codes greater than two are combined in a manner which produces one or more I and Q uncorrelated orthogonal pairs of resulting combined PN sequences. At least two of the component codes in a resulting combined PN sequence are combined in a manner which produces an overall imbalance of ones and zeros in the binary expression of the resulting combined PN sequence so that the resulting composite code has a partial correlation with a predetermined one of the PN component codes. In the preferred embodiment, three component codes are combined to produce uncorrelated orthogonal pairs of composite codes wherein at least one of the pairs of composite codes is produced to have a partial correlation with one or more of the component codes.

7430263, Sep 30, 2008

May 6, 2004

10/840521

Patricia F. Batzer - North Salt Lake City UT, US
Michael L. Wilson - West Valley City UT, US
LaMar K. Timothy - Kaysville UT, US

H04L 7/00

375367, 370515

A timing correction system for fast PN acquisition is provided. The system includes a signal sampler for testing any incoming signal and a real-time clocker coupled to the signal sampler. A parallel correlator is coupled to the real-time clocker for searching for a PN sequence and a burst detector is coupled to the parallel correlator. A chip timing corrector is coupled to the burst detector and a processor is coupled to the chip timing corrector for determining signal timing.

5018170, May 21, 1991

Nov 21, 1989

7/440006

Michael L. Wilson - Salt Lake City UT

Unisys Corporation - Blue Bell PA

H03D 324

375120

A novel digital variable rate clock synthesizer is provided with a novel fractional-N digital phase locked loop. The all digital phase locked loop employs a digital input signal to a phase comparator which has a second input coupled to a digital control oscillator through a divide by N or a divide N+1 circuit. The digital output of the phase comparator is coupled to an error accumulating circuit which has a phase correction input signal from a fractional register and an associated accumulator. The output from the error accumulator is coupled to a pair of detectors for generating phase and frequency error detection signals which are digitally coupled to the control input of the digital control oscillator to provide a variable frequency output selected by the value of N and N+1.

5559788, Sep 24, 1996

Dec 29, 1994

8/366198

John W. Zscheile - West-Farmington UT
Michael L. Wilson - Salt Lake City UT
Richard J. Saggio - Salt Lake City UT
Alan E. Lundquist - Salt Lake City UT

Unisys Corporation - Blue Bell PA

H04J 1300

370 18

A transmitter is provided which simultaneously transmits waveforms such as with different data rates. These transmissions are modulated (e. g. phase modulated) onto quadrature channels of a common carrier, and are then combined. The resulting composite modulated waveform is upconverted to RF, power amplified, split and routed to separate ports for transmission. The transmitted signals are then received, downconverted and demodulated to produce the original signals.

7639725, Dec 29, 2009

Mar 26, 2004

10/811006

Michael L. Wilson - West Valley City UT, US
Merle L. Keller - Salt Lake City UT, US
Vaughn L. Mower - Bountiful UT, US
Kent R. Bruening - Sandy UT, US

H04B 1/69, H04B 1/707

375130, 375141

A phase division multiple access (PDMA) system is provided. The PDMA system includes at least one receiver logic combiner adapted to generate a plurality of composite PN codes. Each of the plurality of composite PN codes are derived from a common composite PN code and are separated by a predetermined PN phase.