Michael Francis Sullivan
Engineers at Hubbells Fls Dr, Essex Junction, VT
License number
Colorado 43659
Issued Date
Nov 17, 2009
Renew Date
Feb 11, 2016
Expiration Date
Oct 31, 2017
Type
Professional Engineer
Address
Address
12 Hubbells Falls Dr, Essex Junction, VT 05452
Professional information
Method Of Performing Parasitic Extraction For A Multi-Fingered Transistor
US Patent:
6519752, Feb 11, 2003
Filed:
Apr 28, 2000
Appl. No.:
09/561096
Inventors:
William C. Bakker - Poughkeepsie NY
Peter A. Habitz - Hinesburg VT
Judith H. McCullen - Essex Junction VT
Edward W. Seibert - Richmond VT
Michael J. Sullivan - Essex Junction VT
Peter A. Habitz - Hinesburg VT
Judith H. McCullen - Essex Junction VT
Edward W. Seibert - Richmond VT
Michael J. Sullivan - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 14
Abstract:
A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.
Performance Optimizing Compiler For Building A Compiled Sram
US Patent:
6002633, Dec 14, 1999
Filed:
Jan 4, 1999
Appl. No.:
9/225075
Inventors:
Jeffery H. Oppold - Richmond VT
Michael R. Ouellette - Westford VT
Michael J. Sullivan - Essex Junction VT
Michael R. Ouellette - Westford VT
Michael J. Sullivan - Essex Junction VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 800, G11C 1100
US Classification:
36523003
Abstract:
A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.