MICHAEL FARRELL, MD
Osteopathic Medicine at Federal Hwy, Fort Lauderdale, FL

7725079, May 25, 2010

Jun 9, 2006

11/450543

Andrew Joo Kim - Atlanta GA, US
Edward Gebara - Atlanta GA, US
Bruce C. Schmukler - Duluth GA, US
Mark W. Dickmann - Palm Harbor FL, US
Michael F. Farrell - Atlanta GA, US
Michael G. Vrazel - Chamblee GA, US
David Anthony Stelliga - Palo Alto CA, US
Joy Laskar - Marietta GA, US
Charles E. Summers - Woodstock GA, US

Quellan, Inc. - Atlanta GA

H04B 1/00, H04B 15/00

455 631, 455570, 4551142, 455222, 4552263

Signals propagating on an aggressor communication channel can cause detrimental interference in a victim communication channel. A signal processing circuit can generate an interference cancellation signal that, when applied to the victim communication channel, cancels the detrimental interference. The signal processing circuit can dynamically adjust or update two or more aspects of the interference cancellation signal, such as an amplitude or gain parameter and a phase or delay parameter. Via the dynamic adjustments, the signal processing circuit can adapt to changing conditions, thereby maintaining an acceptable level of interference cancellation in a fluctuating operating environment. A control circuit that implements the parametric adjustments can have at least two modes of operation, one for adjusting the amplitude parameter and one for adjusting the phase parameter. The modes can be selectable or can be intermittently available, for example.

6114840, Sep 5, 2000

Sep 17, 1998

9/154995

Michael Francis Farrell - Atlanta GA
Paul Edwin Platt - Duluth GA

Integrated Device Technology, Inc. - Santa Clara CA

H03K 1704

322374

Signal transfer devices enable multiple processors to act as drivers or receivers of signals which can transition from an invalid state to a valid state and then return to the invalid state in one clock cycle. The preferred signal transfer device includes a bus line, a plurality of bus drivers electrically connected to the bus line for initiating wired-OR signal transitions and at least one self-timed booster circuit electrically connected to the bus line. The self-timed booster circuit includes a first field effect transistor electrically connected in series between the bus line and a first reference potential and a second field effect transistor electrically connected in series between the bus line and a second reference potential. A timing circuit is also provided as a plurality of inverters which are electrically coupled in series. The timing circuit, which has an input electrically coupled to the bus line, performs a boolean inversion of the signals on the bus line after a first delay.