Michael Dominic James
Electrician at Deerfield Dr, Longmont, CO

6401168, Jun 4, 2002

Jan 4, 1999

09/225124

John W. Williams - Longmont CO
Michael James - Longmont CO

Texas Instruments Incorporated - Dallas TX

G06F 1200

711112, 711105, 711129, 714773, 714769

A mass data storage device ( ) and method for operating it are disclosed. The mass data storage device has a rotating disk memory ( ) which has a number of sectors for containing data. A FIFO memory ( ) has three memory sections ( ), each for containing an entire sector of data associated with respective sectors of the rotating disk memory. An ECC unit ( ) has random access to any data contained in the FIFO memory ( ). The ECC unit ( ) is operated to perform error correction on data while the data is contained in the FIFO memory ( ). A FIFO memory controller ( ) controls locations at which data is written into and read from the FIFO memory ( ), and locations at which data correction is performed by the ECC unit ( ), so that as data is written into a first portion of the memory containing a sector currently being written, the ECC unit concurrently accesses a second portion of the memory containing a sector previously written to correct data therein, and data that has already been corrected by the ECC unit in a third portion of the memory is concurrently being read from the memory.

6747827, Jun 8, 2004

Mar 27, 2000

09/536282

Stephen J. Bassett - Ft. Collins CO
Daniel Woods - Longmont CO
Michael James - Longmont CO

Texas Instruments Incorporated - Dallas TX

G11B 509

360 53, 360 39

A method for performing error correction code operations on data to be read from the disk ( ) of a hard disk drive ( ) includes applying a first error correction code algorithm to a first set of data to be written to the hard disk drive, and a second error correction code algorithm, different from the first, to a second set of data to be written to the hard disk drive ( ). The first and second error correction code algorithms may for example produce a different number of error correction code bits for application to said data. The selection between the first and second algorithms may be made, for instance, in dependence upon the physical locations ( ) on the disk, or in dependence upon the type of said data ( ) to be written. By reducing the number of ECC bits that need be associated with at least some of the data to be written to the disk ( ), the available space on the disk for user data can be increased.

7191382, Mar 13, 2007

Jun 2, 2003

10/452603

Michael James - Longmont CO, US
Kana Ono - Longmont CO, US

Fujitsu Limited - Kawasaki

G11C 29/00

714769

When data is read from a disk and stored in volatile memory, check bits are generated and stored in the memory using an algorithm such as cyclical redundancy check (CRC). The CRC algorithm operates on the basis of the bit length in which the data is organized, such as 8 bits. If the data has errors, an error correction code (ECC) algorithm is used to correct the data errors, but the ECC algorithm operates on the basis of symbols having a different bit length, such as 10 bits. To avoid having to re-read the data from the volatile memory to adjust the CRC value, the CRC algorithm is executed on selected mask data developed by the ECC algorithm, the CRC algorithm being executed on the basis of the second bit length to generate a CRC mask. The CRC mask corrects the stored CRC value.

7213192, May 1, 2007

Sep 8, 2004

10/936069

Michael James - Longmont CO, US

Fujitsu Limited - Kawasaki

G11B 20/18

714769

Data requested from a disk drive by a host is read continuously from sectors in tracks on a rotating disk and is temporarily stored in buffer memory within the disk drive. Before releasing the sectors for host access, each sector is checked for errors, and if errors are identified, error correction is attempted in a correction engine, using a selected error correction facility. If the errors are not corrected using the first selected correction facility, the bad sector is held in the buffer memory until the correction engine is idle. The correction engine is idle, for example, when good sectors (which have no errors) are read and are immediately released for host access. This idle time in the correction engine is used to attempt error correction using one or more different correction facilities. If the errors are corrected using the correction engine's idle time, it is not necessary to re-read the sector.

2010001, Jan 14, 2010

Jul 9, 2008

12/170306

Jason Molgaard - Windsor CO, US
Michael James - Longmont CO, US
Bradford Lincoln - Boulder CO, US

FUJITSU LIMITED - Kawasaki-shi

G06F 13/18, G06F 12/00

711151, 711E12001

A microcontroller system includes at least one processor and at least one storage unit for storing data received from or to be sent to the processor. At least two read clients are provided in the processor for retrieving data from the storage unit, and at least one write client is provided in the processor for writing data in the storage unit. The system further includes a memory device provided in the storage unit for storing data, and an arbitration device provided in the storage unit for enabling access to the memory device by the read and the write client. The read clients each have a dedicated read address line connected to the arbitration device for sending a read address of read data to be retrieved from the memory device, and a shared read data bus connected to the memory device for receiving the read data from the read address.

2008015, Jun 26, 2008

Dec 22, 2006

11/644052

Michael James - Longmont CO, US
Bradford C. Lincoln - Boulder CO, US
Jason Molgaard - Windsor CO, US

G06F 1/00

713500

Apparatus for controlling input clock signals to a microprocessor includes a clock generator for generating the input clock signals to the microprocessor, and a clock controller for producing a control signal for disabling the clock generator from outputting the input clock signals to the microprocessor for a predetermined time. The clock generator resumes outputting the input clock signals to the microprocessor after the predetermined time.

2008030, Dec 11, 2008

Jun 7, 2007

11/810821

Michael James - Longmont CO, US
Scott Richmond - Boulder CO, US

G06F 7/38

712228, 712E09001

An application specific processor executes multiple dedicated applications in a system having a main control processor for controlling the operation of the system. The application specific processor includes a first context for executing a corresponding first application and a second context for executing a corresponding second application. An instruction memory outputs instructions for executing the first and second applications, and a context switch instruction for switching from one context to the other context. Context is switched in response to the context switch instruction while executing the first or second application.

2009018, Jul 16, 2009

Jan 11, 2008

12/008633

Michael James - Longmont CO, US
Scott Richmond - Boulder CO, US

Fujitsu Limited - Kawasaki-shi

G11B 5/09

360 48

A disk formatter in a disk drive having a main control processor for performing functions relating to transfer of data between a host and at least one disk medium, includes a processor for obtaining sector information of a target sector on the disk medium and issuing commands for reading or writing data on the target sector based on the sector information. A command receiving unit receives the commands for reading or writing issued by the processor and enables reading or writing of the target sector, and a routing unit receives data or status information from the target sector and communicates the data or status information to the processor for enabling the processor to adjust the commands for reading and writing data on the disk sectors based on the data or status information and the sector information.

2009029, Nov 26, 2009

May 22, 2008

12/125683

Jason Molgaard - Windsor CO, US
Michael James - Longmont CO, US
Bradford Lincoln - Boulder CO, US

FUJITSU LIMITED - Kawasaki-shi

G06F 12/14

711152, 711E12098

Apparatus for controlling atomic access to a memory includes an access request evaluator for receiving an atomic access request to an address in the memory from a client and determining whether to allow atomic access to the requested address. An access indicator indicates whether a select address is currently under atomic access in the memory, and an access release indicates whether the atomic access is completed at the select address. The access request evaluator enables the client atomic access to the requested address if the access indicator indicates that the requested address is currently not under atomic access.

2010030, Dec 2, 2010

May 27, 2009

12/472696

Michael James - Longmont CO, US
Darren Lasko - Longmont CO, US
John W. Williams - Longmont CO, US

FUJITSU LIMITED - Kawasaki-shi

H04L 9/06, G06F 12/02, H04L 9/28

380277, 711103, 711E12008, 713189

A system-on-chip control system includes a processor for generating a root key for protecting data stored in a memory device connected to the control system, a root key storage unit for storing the root key, and a debug port configured to enable an external device to access the control system. The processor keeps the debug port locked to prevent the external device from accessing the control system if a root key is stored in the storage unit, and unlocks the debug port to enable the external device to access the control system after the root key is erased.