MICHAEL DIXON BARRY, LMT
Massage Therapy at Tillamook St, Portland, OR
License number
Oregon 23043
Category
Restorative Service Providers
Type
Massage Therapist
Address
Address
4423 NE Tillamook St, Portland, OR 97213
Phone
(503) 707-1715
Personal information
See more information about MICHAEL DIXON BARRY at radaris.comName
Address
Phone
274 Park Dr, Shady Cove, OR 97539
745 Koos Bay Blvd, Coos Bay, OR 97420
1895 Archer Dr, Medford, OR 97501
Professional information
Retired From Federal Govt, Human Resource Management
Position:
Labor and Employee Relations Specialist at Portland Va Medical Center
Location:
Portland, Oregon Area
Industry:
Hospital & Health Care
Work:
Portland Va Medical Center
- Portland, Oregon Area since Jul 1994
-
Labor and Employee Relations Specialist
Portland VA Medical Center
Oct 2006 - Jun 2013
-
Personnel Security Program Manager
Portland VA Medical Center
Dec 1999 - Sep 2006
-
Information Security Officer
Education:
George Fox University 1991 - 1993
BA, Human Resource Management
BA, Human Resource Management
Michael Barry - Portland, OR
Work:
Families for Depression Awareness - Waltham, MA
Marketing Coordinator Veggie Galaxy - Cambridge, MA
Server, Host, Barista The Small Planet Institute - Cambridge, MA
Summer Communications Intern Partners In Health - Boston, MA
Design, Communications, & Outreach Intern eCul De Sac - Boston, MA
Marketing & Media Intern Boston University Community Service Center - Boston, MA
Service Project Coordinator Boston University Educational Resource Center - Boston, MA
Office Assistant The Boston Phoenix - Boston, MA
Editorial & Web Intern Boston University Orientation - Boston, MA
Orientation Leader Boston University Residence Life - Boston, MA
Resident Assistant
Marketing Coordinator Veggie Galaxy - Cambridge, MA
Server, Host, Barista The Small Planet Institute - Cambridge, MA
Summer Communications Intern Partners In Health - Boston, MA
Design, Communications, & Outreach Intern eCul De Sac - Boston, MA
Marketing & Media Intern Boston University Community Service Center - Boston, MA
Service Project Coordinator Boston University Educational Resource Center - Boston, MA
Office Assistant The Boston Phoenix - Boston, MA
Editorial & Web Intern Boston University Orientation - Boston, MA
Orientation Leader Boston University Residence Life - Boston, MA
Resident Assistant
Education:
Boston University - Boston, MA
BA in Anthropology Boston University - Boston, MA
BS in Journalism
BA in Anthropology Boston University - Boston, MA
BS in Journalism
Delivery Center Security Engineer At Presidio
Location:
Portland, Oregon Area
Industry:
Information Technology and Services
High Reliability Logic Circuit For Radiation Environment
US Patent:
5870332, Feb 9, 1999
Filed:
Apr 22, 1996
Appl. No.:
8/635794
Inventors:
Michael D. Lahey - Colorado Springs CO
Debra S. Harris - Colorado Springs CO
Harry N. Gardner - Colorado Springs CO
Michael J. Barry - Tigard OR
Debra S. Harris - Colorado Springs CO
Harry N. Gardner - Colorado Springs CO
Michael J. Barry - Tigard OR
Assignee:
United Technologies Corporation - Hartford CT
International Classification:
G11C 1140
US Classification:
365156
Abstract:
A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states.
The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell.
The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit. The summing of the output signals from the first and second memory cell prevents a single error in either memory cell from propagating to a next stage.