Michael Dean Clark
Engineering at Fulbright Ln, Austin, TX

6446189, Sep 3, 2002

Jun 1, 1999

09/323321

Frederick D. Weber - San Jose CA
William A. Hughes - Burlingame CA
William K. Lewchuk - Austin TX
Scott A. White - Austin TX
Michael T. Clark - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1200

711207, 711209, 710 49

A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e. g. , a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU. The BIU includes address translation circuitry, a multiplexer, and gating logic, and returns the physical address corresponding to the linear address to the cache unit.

6446215, Sep 3, 2002

Aug 20, 1999

09/378026

Derrick R. Meyer - Austin TX
Scott A. White - Austin TX
Michael T. Clark - Austin TX
Philip E. Madrid - Round Rock TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 126

713310, 713322, 713323, 710262, 710267

A method and apparatus for controlling power management state transitions between two devices, e. g. , a processor and a bus bridge, that are connected through a clock forwarded interface bus in a computer system. The bus bridge is configured to coordinate disconnection of the processor from the interface. Particularly, the bus bridge may use a fist signal to indicate whether or not the processor is to be disconnected from the interface (e. g. a CONNECT signal) and the processor may use a second signal to indicate whether or not the processor is to be disconnected from the interface (e. g. a PROCREADY signal). The processor is disconnected from the interface responsive to both the first signal and the second signal indicating that the processor is to be disconnected. The signals may also be used to reconnect the processor to the interface.

2009003, Feb 5, 2009

Aug 1, 2007

11/831985

Michael T. Clark - Austin TX, US
Jelena Ilic - Austin TX, US

G06F 9/44, G06F 13/24, G06F 15/177, G06F 15/76

719315, 710267, 712 30, 713 2, 712E09038

A computer system includes a system memory, a plurality of processor cores, and an input/output (I/O) hub that may communicate with each of the processor cores. In response to detecting an occurrence of an internal system management interrupt (SMI), each of the processor cores may save to a system management mode (SMM) save state in the system memory, information corresponding to a source of the internal SMI. In response to detecting the internal SMI, each processor core may further initiate an I/O cycle to a predetermined port address within the I/O hub. The I/O hub may broadcast an SMI message to each of the processor cores in response to receiving the I/O cycle. Each of the processor cores may further save to the SMM save state in the system memory, respective internal SMI source information in response to receiving the broadcast SMI message.

7373484, May 13, 2008

Jan 12, 2004

10/755692

Arun Radhakrishnan - Austin TX, US
Benjamin T. Sander - Austin TX, US
Michael A. Filippo - Manchaca TX, US
Michael T. Clark - Austin TX, US
David E. Kroesche - Round Rock TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9/30

712217, 712218

A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.