Michael Alan Lee
Respiratory Therapy at Beebrush Ln, Austin, TX

2006003, Feb 23, 2006

Aug 19, 2004

10/922247

Sam Chu - Round Rock TX, US
Peter Klim - Austin TX, US
Michael Lee - Austin TX, US
Jose Paredes - Austin TX, US

International Business Machines Corporation - Armonk NY

G11C 7/10

365189040, 365189120, 365189050

A register file apparatus and method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.

2004025, Dec 9, 2004

Jun 5, 2003

10/455163

Sam Chu - Round Rock TX, US
Peter Klim - Austin TX, US
Michael Lee - Austin TX, US
Jose Paredes - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F007/38, H03K019/173, G01R031/28

714/726000

According to one form, a latch has an output node and sublatches. The sublatches each have an output node coupled to input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and to generate output signals on their respective output nodes. At least one sublatch output node is coupled to the latch output node. The output nodes of other ones of the sublatches are connected in the latch such that if any one of the sublatches is subjected to a radiation induced erroneous change of state the output signals of the other sublatches reduce an effect of the change on the latch output signal. The latch also includes a number of scanning-mode control switches coupled to ones of the sublatches for scanning data in or out.

2005020, Sep 22, 2005

Mar 18, 2004

10/803588

Jason Cantin - Madison WI, US
Michael Lee - Austin TX, US

INTERNATIONAL BUSINESS MACHINES CORP. - Armonk NY

H03K019/096

327217000

A latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits is disclosed. The latch circuit includes four separate logic gates. The first inputs of the first and second logic gates are connected to a first and second precharged internal nodes of the dynamic logic circuit, respectively. The second inputs of the first and second gates are connected to a first and second differential outputs of the dynamic logic circuit, respectively. The first inputs of the third and fourth gates are connected to an output of the first and second logic gates, respectively. The second input of the fourth gate is connected to an output of the third logic gate to provide a first output for the latch circuit. Similarly, the second input of the third logic gate is connected to the output of the fourth logic gate to provide a second output for the latch circuit.

7561489, Jul 14, 2009

May 22, 2008

12/125875

Michael J. Lee - Austin TX, US
Jose A. Paredes - Austin TX, US
Peter J. Klim - Austin TX, US
Sam G. Chu - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G11C 8/00

36523006, 36518905, 36523008

A system and method of selective row energization based on write data, with a selective row energization system including a storage array having M rows and N columns ; an N-bit data word register ; a uniform-detect circuit responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register having M uniform-detect latches , each being associated with one of the M rows and storing the uniform word data bit for the data word stored in the associated M row ; and an M-bit row driver device responsive to the uniform word data bit for each of the M rows to inhibit energization of the M rows for which the uniform word data bit is the first value.

7788444, Aug 31, 2010

Dec 12, 2006

11/609464

Michael J. Lee - Austin TX, US
Bao G. Truong - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 13/00, G06F 13/28, G11C 15/00

711108, 365 4917

Mechanisms for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.

7304352, Dec 4, 2007

Apr 21, 2005

11/111454

K. Paul Muller - Wappingers Falls NY, US
Kevin A. Batson - Williston VT, US
Michael J. Lee - Austin TX, US

International Business Machines Corporation - Armonk NY

H01L 29/76, H01L 29/94

257369, 257202, 257903, 257904, 257296, 257300, 257508, 257E27099, 257E27101, 257E21661, 365 63, 365154

A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.

7379348, May 27, 2008

Jan 26, 2006

11/340535

Michael J. Lee - Austin TX, US
Jose A. Paredes - Austin TX, US
Peter J. Klim - Austin TX, US
Sam G. Chu - Round Rock TX, US

Internatioanl Business Machines Corporation - Armonk NY

G11C 7/00

365189011, 36523006

A system and method of selective row energization based on write data, with a selective row energization system including a storage array having M rows and N columns ; an N-bit data word register ; a uniform-detect circuit responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register having M uniform-detect latches , each being associated with one of the M rows and storing the uniform word data bit for the data word stored in the associated M row ; and an M-bit row driver device responsive to the uniform word data bit for each of the M rows to inhibit energization of the M rows for which the uniform word data bit is the first value.