MICHAEL ADAM SNYDER
Pilots at Burton Dr, Austin, TX

6785772, Aug 31, 2004

Apr 26, 2002

10/132918

Suresh Venkumahanti - Austin TX
Michael Dean Snyder - Austin TX

Freescale Semiconductor, Inc. - Austin TX

G06F 1200

711137, 711128, 711158, 711213, 712207

A data processing system ( ) is able to perform parameter-selectable prefetch instructions to prefetch data for a cache ( ). When attempting to be backward compatible with previously written code, sometimes performing this instruction can result in attempting to prefetch redundant data by prefetching the same data twice. In order to prevent this, the parameters of the instruction are analyzed to determine if such redundant data will be prefetched. If so, then the parameters are altered to avoid prefetching redundant data. In some of the possibilities for the parameters of the instruction, the altering of the parameters requires significant circuitry so that an alternative approach is used. This alternative but slower approach, which can be used in the same system with the first approach, detects if the line of the cache that is currently being requested is the same as the previous request. If so, the current request is not executed.

7681021, Mar 16, 2010

Sep 28, 2006

11/536173

Sergio Schuler - Austin TX, US
Michael D. Snyder - Austin TX, US
Leick D. Robinson - Round Rock TX, US
David M. Thompson - Arlington TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 9/00, G06F 1/32

712238, 713324

A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after a fetch of a branch. Thus, for a first branch, for example, a first wake number is predicted. A low power mode of the branch predictor is enabled for a duration of the first wake value in response to hit in the branch target buffer in which the hit is in response to the first branch.

7805581, Sep 28, 2010

Feb 27, 2007

11/679590

Michael D. Snyder - Austin TX, US
David C. Holloway - Cedar Park TX, US
Trinh H. Nguyen - Round Rock TX, US
Sergio Schuler - Austin TX, US
Gary L. Whisenhunt - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 12/00

711154, 711170, 711E12084

A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

6163835, Dec 19, 2000

Jul 6, 1998

9/110351

David William Todd - Austin TX
Michael Dean Snyder - Austin TX
Brian Keith Reynolds - Round Rock TX
Michael Julio Garcia - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1516

712 34

A method of transferring data between a slave device (20) in communication with a processor interface bus (34) where the processor interface bus is in communication with a master device (12) including receiving an address from the processor interface bus (34) where the address was provided by the master device (block 302). A first signal is asserted (blocks 318 and 324) on the processor interface bus (34) to indicate that the slave device (20) is servicing a data transfer transaction. A second signal is asserted (block 320) on the processor interface bus (34) to indicate whether data to be transferred using the processor interface bus (34) is to be stored in main memory (36) by a main memory controller (32) in communication with the processor interface bus (34). The data is transferred (block 326) between the slave device (20) and the processor interface bus (34).

2009001, Jan 15, 2009

Jul 11, 2007

11/776267

Sanjay R. Deshpande - Austin TX, US
Bryan D. Marietta - Austin TX, US
Michael D. Snyder - Austin TX, US
Gary L. Whisenhunt - Austin TX, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

G06F 12/08

711141, 711E12026

A processing system includes a plurality of coherency domains and a plurality of coherency agents. Each coherency agent is associated with at least one of the plurality of coherency domains. At a select coherency agent of the plurality of coherency agents, an address translation for a coherency message is performed using a first memory address to generate a second memory address. A select coherency domain of the plurality of coherency domains associated with the coherency message is determined at the select coherency agent based on the address translation. The coherency message and a coherency domain identifier of the select coherency domain are provided by the select coherency agent to a coherency interconnect for distribution to at least one of the plurality of coherency agents based on the coherency domain identifier.

8122437, Feb 21, 2012

Mar 31, 2008

12/058874

Zheng Xu - Austin TX, US
Suraj Bhaskaran - Austin TX, US
Klas M. Bruce - Leander TX, US
Jason T. Nearing - Austin TX, US
Paul B. Rawlins - Austin TX, US
Matt B. Smittle - Allen TX, US
Michael D. Snyder - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 9/44, G06F 11/00

717128, 714 35

In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e. g. , a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.

6321303, Nov 20, 2001

Mar 18, 1999

9/271492

Thomas Alan Hoy - Austin TX
Belliappa Manavattira Kuttanna - Sunnyvale CA
Rajesh Patel - Austin TX
Michael Dean Snyder - Austin TX

International Business Machines Corporation - Armonk NY

G06F 1208

711140

A computer and its corresponding cache system includes a cache memory, a buffer unit, and a bus transaction queue. The buffer unit includes a plurality of entries suitable for temporarily storing data, address, and attribute information of operations generated by the CPU. A first operation initiated by the load store unit buffers an operation in a first entry of the buffer unit, which initiates a first transaction to be queued in a first entry of the bus transaction queue where the first transaction in the bus transaction queue points to the first entry in the buffer unit. Preferably, the buffer unit is configured to modify the first transaction from a first transaction type to a second transaction type prior to execution in response to an event that alters the data requirements of the queued transaction. Additional utility is achieved by merging multiple store operation that miss to a common cache line into a single entry. Further benefits is achieved by allowing multiple load misses to the same cache line to be completed from a buffer that reduces cache pipeline stalls.

7827360, Nov 2, 2010

Aug 2, 2007

11/832797

Syed R. Rahman - Austin TX, US
David F. Greenberg - Austin TX, US
Kathryn C. Stacer - Round Rock TX, US
Klas M. Bruce - Leander TX, US
Matt B. Smittle - Allen TX, US
Michael D. Snyder - Austin TX, US
Gary L. Whisenhunt - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G06F 12/00

711141, 711143, 711144, 711163

A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.

6073215, Jun 6, 2000

Aug 3, 1998

9/127884

Michael Dean Snyder - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1208

711137

A data processing system (10) includes a mechanism for preventing DST line fetches from occupying the last available entries in a cache miss queue (50) of the data cache and MMU (16). This is done by setting a threshold value of available cache miss queue (50) buffers over which a DST access is not allowed. This prevents the cache miss queue (50) from filling up and preventing normal load and store accesses from using the cache miss queue (50).