MATTHEW W. WALKER, M.D.
Anesthesiologist Assistant at Colchester Ave, Burlington, VT
License number
Vermont 0420010772
Category
Osteopathic Medicine
Type
Anesthesiology
Address
Address
111 Colchester Ave, Burlington, VT 05401
Phone
(802) 847-2415
(802) 847-5324 (Fax)
(802) 847-5324 (Fax)
Personal information
See more information about MATTHEW W. WALKER at radaris.comName
Address
Phone
4 Moss Glen Ln, South Burlington, VT 05403
499 Lake Rd, Charlotte, VT 05445
Professional information
School Crew Leader At Vermont Youth Conservation Corps
Position:
School Crew Leader at Vermont Youth Conservation Corps
Location:
Burlington, Vermont Area
Industry:
Education Management
Work:
Vermont Youth Conservation Corps
-
School Crew Leader
Matthew Wendell Walker, Burlington VT
Specialties:
Anesthesiology, Allergy & Immunology, Radiology
Work:
Fletcher Allen Health Care
111 Colchester Ave, Burlington, VT 05401 Sutter General Hospital
2801 L St, Sacramento, CA 95816 Central Anesthesia Svc
3315 Watt Ave, Sacramento, CA 95821
111 Colchester Ave, Burlington, VT 05401 Sutter General Hospital
2801 L St, Sacramento, CA 95816 Central Anesthesia Svc
3315 Watt Ave, Sacramento, CA 95821
Education:
Wake Forest University (1999)
Dr. Matthew W Walker, Burlington VT - MD (Doctor of Medicine)
Specialties:
Anesthesiology
Address:
111 Colchester Ave, Burlington 05401
(802) 847-2415 (Phone), (802) 847-5324 (Fax)
CASE MEDICAL GROUP
3315 Watt Ave, Sacramento 95821
(916) 481-6800 (Phone), (916) 481-1881 (Fax)
(802) 847-2415 (Phone), (802) 847-5324 (Fax)
CASE MEDICAL GROUP
3315 Watt Ave, Sacramento 95821
(916) 481-6800 (Phone), (916) 481-1881 (Fax)
Certifications:
Anesthesiology, 2004
Awards:
Healthgrades Honor Roll
Languages:
English
Hospitals:
111 Colchester Ave, Burlington 05401
CASE MEDICAL GROUP
3315 Watt Ave, Sacramento 95821
Fletcher Allen Health Care
111 Colchester Ave, Burlington 05401
CASE MEDICAL GROUP
3315 Watt Ave, Sacramento 95821
Fletcher Allen Health Care
111 Colchester Ave, Burlington 05401
Education:
Medical School
Wake Forest University
Graduated: 1999
Wake Forest University
Graduated: 1999
Vermont Department Of Public Service
Position:
Planning and Energy Resources Division at Vermont Department of Public Service
Location:
Burlington, Vermont Area
Industry:
Public Policy
Work:
Vermont Department of Public Service
- Montpelier, Vermont since Jun 2011
-
Planning and Energy Resources Division
Vermont Youth Conservation Corps
Aug 2008 - Jul 2010
-
Conservation and Environmental Education
Education:
Vermont Law School 2010 - 2011
Masters of Environmental Law and Policy, Environmental Law and Policy (Energy Policy)
Masters of Environmental Law and Policy, Environmental Law and Policy (Energy Policy)
Tool And Method To Graphically Correlate Process And Test Data With Specific Chips On A Wafer
US Patent:
8234597, Jul 31, 2012
Filed:
Jan 14, 2008
Appl. No.:
12/013533
Inventors:
Mark J. Flemming - Essex Junction VT, US
Alexander J. Franz - Westford VT, US
Tyler D. Kieft - Essex Junction VT, US
Raghav Kohli - Essex Junction VT, US
Karl V. Swanke - Essex Junction VT, US
Matthew S. Turnbull - Essex Junction VT, US
Matthew Walker - South Burlington VT, US
Alexander J. Franz - Westford VT, US
Tyler D. Kieft - Essex Junction VT, US
Raghav Kohli - Essex Junction VT, US
Karl V. Swanke - Essex Junction VT, US
Matthew S. Turnbull - Essex Junction VT, US
Matthew Walker - South Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 51, 716 50
Abstract:
A tool and method is provided to graphically correlate process and test data with specific chips on a multi-project wafer. The tool and method is configured and implemented to select certain sites and export these sites to an industry standard map that can be used in a variety of chip picking or test tools. In one embodiment, the method includes importing a wafer floor plan with chips of different design parameters and importing manufacturing logistical information of the chips. The method further includes graphically rendering each chip on the wafer to scale within a unit cell using the imported wafer floor plan and the manufacturing logistical information.