MARVIN A MARTINEZ
Electrician at Raintree Dr, Plano, TX

5611071, Mar 11, 1997

Apr 19, 1995

8/425939

Marvin W. Martinez - Plano TX

Cyrix Corporation - Richardson TX

G06F 1208

395460

A procedure for implementing cache line replacement cycle as split replacement cycles is used in a 64/32 computer system including a 64-bit x86 microprocessor interfaced to a 32-bit x86 bus architecture which does not support pipelined bus cycles. The microprocessor includes an internal L1 cache with two sectors S0 and S1 per cache line such that a cache line replacement request involving both sectors is performed as a split replacement cycle with a separate burst write cycle for each sector. The microprocessor's bus interface unit (BIU) includes (a) a BCC register which is used to stage the first sector (S0) of a split replacement cycle as the current bus cycle, and (b) a BNC register, which is used in a pipelined 64-bit bus architecture to stage pipelined bus cycles, but is used in the exemplary 64/32 system to stage the second sector (S1) of the split replacement cycle. For normal split replacement cycles, the BIU (a) runs the first burst write cycle to transfer S0 from BCC, (b) transfers the S1 to BCC, and (c) runs the second burst write cycle. If the first burst write cycle is interrupted by BOFF#, and if the cache inquiry hits on S1 in BNC, the BIU implements a combined replacement/snoop write-back cycle with sector reordering by (a) running the snoop write-back cycle to transfer S1 from BNC, and (b) rerunning the first bus cycle to transfer S0 from BCC.

5664149, Sep 2, 1997

Nov 12, 1993

8/151489

Marvin Wayne Martinez - Plano TX
Mark W. Bluhm - Plano TX
Jeffrey S. Byrne - Plano TX
David A. Courtright - Richardson TX
Douglas Ewing Duschatko - Plano TX
Raul A. Garibay - Richardson TX
Margaret R. Herubin - Coppell TX

Cyrix Corporation - Richardson TX

G06F 1200

711141

A write-back coherency system, including FLUSH/INVAL and LOCK protocols, is used, in an exemplary embodiment, in a microprocessor used in a computer system that selectively provides to the processor FLUSH and INVAL signals to implement a limited write-back protocol. The FLUSH/INVAL protocol is used by the computer system to control export and invalidate operations. In response to a FLUSH signal, the microprocessor exports dirty data from the cache. If INVAL is also asserted, the cache is also invalidated (i. e. , if FLUSH is asserted and INVAL is not asserted, no invalidation is performed). With the LOCK protocol, LOCKed reads are serviced out of the cache for read hits--however, to maintain compatibility with computer systems that expect a LOCK operation to involve a read followed by a write access to external memory, the microprocessor will still run the external LOCKed read cycle, ignoring the returned data.

5524234, Jun 4, 1996

Dec 28, 1994

8/365972

Marvin W. Martinez - Plano TX
Mark Bluhm - Carrollton TX
Jeffrey S. Byrne - Garland TX
David A. Courtright - Richardson TX
Douglas E. Duschatko - Plano TX
Raul A. Garibay - Plano TX
Margaret R. Herubin - Coppell TX

Cyrix Corporation - Richardson TX

G06F 1216, G06F 1316, G06F 1328

395468

A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master. The X%DIRTY function provides write-back latency control by dynamically switching the cache from write-back to write-through mode if a cache write would cause the number of cache locations containing dirty data to exceed a predetermined maximum percentage of the total number of cache locations.

5860111, Jan 12, 1999

Jun 29, 1995

8/496712

Marvin Wayne Martinez - Plano TX
Mark Bluhm - Carrollton TX
Jeffrey S. Byrne - Garland TX
David A. Courtright - Richardson TX
Douglas Ewing Duschatko - Plano TX
Raul A. Garibay - Plano TX
Margaret R. Herubin - Coppell TX

National Semiconductor Corporation - Santa Clara CA

G06F 1208

711143

A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master.

5596731, Jan 21, 1997

Apr 21, 1995

8/426300

Marvin W. Martinez - Plano TX
Mark W. Bluhm - Plano TX

Cyrix Corporation - Richardson TX

G06F 1338

395309

A single block bus transfer (SCBT) protocol is implemented, in an exemplary embodiment, in a computer system that includes an. times. 86 microprocessor, system logic, and an external memory subsystem including L2 cache and system DRAM, intercoupled by a 586 bus architecture. The microprocessor's bus interface unit (BIU) includes SCBT logic that generates internal effective BRDY# and the effective KEN# signals from either (a) L2. sub. -- HIT from the L2 cache, or (b) BRDY# or KEN# from the system logic. The effective KEN# signal is used for convert a potentially cacheable read into a burst fill cycle. The exemplary L2 cache is able to perform address decode and cache look-up in time to return L2 HIT to the processor during the ADS# clock with sufficient timing margin to permit the processor to complete the bus transfer (either not burst bus cycle, or the first bus transfer of a burst cycle) in that clock and set up for a next bus transfer in the next clock. The BIU uses a forced deadclock mechanism to prevent a single clock bus transfer from being followed in the next clock by a next bus transfer if the result would be consecutive read and write cycles (thereby avoiding device driver contention on the data bus).

5898815, Apr 27, 1999

Feb 13, 1996

8/600781

Mark W. Bluhm - Plano TX
Marvin W. Martinez - Plano TX

National Semiconductor Corporation - Santa Clara CA

G06F 13372

395865

A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.

6122696, Sep 19, 2000

Sep 29, 1997

8/937821

Andrew T. Brown - Ft. Collins CO
Marvin W. Martinez - Plano TX

G06F 1300

710127

A CPU-Peripheral bus interface for 64-bit local bus to 32-bit peripheral bus uses byte enable signaling to provide byte lane steering. Qbuffer logic provides a hardware interface that interfaces directly to the processor local-bus--a Qbuffer protocol using conventional byte enable signals provides lane steering to eliminate the need for separate multiplexing logic. The Qbuffer protocol signals include a BE control signal asserted by the system logic to cause the CPU to relinquish control of the byte enable control lines, such that the system control logic is able to drive the BE control lines with byte enable codes to implement lane steering for CPU-Peripheral transfers.

5742184, Apr 21, 1998

Feb 16, 1996

8/603053

Marvin W. Martinez - Plano TX

Cyrix Corporation - Richardson TX

H03K 190185, H03K 190948

326 83

An input buffer circuit provides programmable resistors for inputs to a microprocessor and compensates for switching voltage timing differences caused when a selected programmable resistor is utilized for a selected input. In a preferred embodiment, an input buffer circuit has a weak transistor coupled between the input and an operating voltage source or ground, and a compensation circuit including two transistors in series between the operating voltage source or ground, and an output. When the weak transistor is on, thereby raising or lowering the input signal, one of the transistors is also on and the other transistor couples the output to the operating voltage source or ground.