MARK WEAVER, PA
Physician Assistant at Agave Rd, Phoenix, AZ

6570916, May 27, 2003

Mar 4, 1997

08/811414

David W. Feldbaumer - Chandler AZ
Mark B. Weaver - Phoenix AZ
Rimon Shookhtim - Mesa AZ
Cecil Aswell - Orangevale CA

Semiconductor Components Industries LLC - Phoenix AZ

H03H 740

375232

A timing based adaptive equalization circuit ( ) dynamically monitors a signal received at an input terminal ( ) and compensates for attenuation losses in the transmission of the signal by adjusting an equalization value that increases or decreases the equalization of the signal. A digital phase locked loop control circuit ( ) centers the transition of the equalized signal in a delay line circuit ( ). An analog delay locked loop circuit ( ) provides a fixed throughput time for matching delay elements of delay line circuits ( and ) in the adaptive equalization circuit ( ). Timing signals propagating in the delay line circuits ( and ) are stored in sampler circuits ( and ). The equalization value for equalizing the input signal is adjusted based on stored logic values of specific storage elements in the sampler circuits ( and ).

5586046, Dec 17, 1996

Oct 28, 1994

8/330463

David Feldbaumer - Chandler AZ
Frederick L. Lum - Scottsdale AZ
Vickie Mercier - Tempe AZ
Mark B. Weaver - Phoenix AZ
Rimon Shookhtim - Mesa AZ

Motorola, Inc. - Schaumburg IL

G06F 1750

364490

A computer implemented method for generating an integrated circuit design (11) is provided. A description of a circuit (16) is provided in a format such as a Hardware Description Language (12). A functional simulation (17) of the description is run to determine functionality of the circuit. A netlist conversion (18) converts the description to a netlist comprising both a single-ended and differential circuit. The netlist conversion (18) converts the description to a single-ended description (24), replaces single-ended cells with differential cells and interconnects the differential cells (25), and exchanges terminals of the differential cells to maintain logic equivalence (26). A simulation with timing (19) is run on the netlist to verify timing characteristics of the circuit. The netlist is then provided to a router to generate a physical circuit layout (20) having both single-ended and differential circuits.

5627492, May 6, 1997

Nov 3, 1995

8/552709

Mark Weaver - Phoenix AZ
Robert D. Berger - Chandler AZ
Dwight D. Esgar - Queen Creek AZ

Motorola, Inc. - Schaumburg IL

G05F 110

327544

An integrated circuit is divided into functional blocks. The integrated circuit includes current source based circuitry such as Emitter Coupled Logic (ECL), Current Mode Logic (CML), or Source Coupled Logic (SCL) Isolation blocks (14-20) are placed in signal paths to and from each functional block. A multiple output bias driver circuit (13) couples to each functional block. The multiple output bias driver circuit (13) provides a signal for enabling and disabling current sources of a functional block. A bias control logic circuit (12) controls the isolation blocks (14-20) and the multiple output bias driver (13). A functional block that is idle in the operation of the integrated circuit is shut down by the bias control logic circuit (12) to conserve power. The multiple output bias driver circuit (13) receives control signals from the bias control logic circuit (12) to turn off current sources in the idle functional block. Isolation blocks (14-20) receive control signals from the bias control logic circuit (12) to isolate the idle functional block and to provide a predetermined logic level in the signal paths from the idle functional to prevent propagation of an erroneous signal.

7061540, Jun 13, 2006

Dec 19, 2001

10/025039

Mark Weaver - Phoenix AZ, US
Bart Decanne - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H04N 5/04

348500, 348177, 348516, 348542, 348543, 348544, 348555, 345698, 345699

A display timing generator is provided for selecting line types and providing synchronization timing signals for video signals. The display timing generator provides programmability for the user to select line types for a frame to be displayed on a display. The line types defining rise and fall times, synchronization shapes, blanking levels and horizontal and vertical timings for providing a desired display format to different display types. A plurality of programmable parameters for pulse width, horizontal timing and voltage amplitude allow a user to define timing variations associated with a given line type. The display timing generator also includes a generic mode for allowing a programmer to select line types for particular groupings of lines.