DR. MARK W TAYLOR, O.D.
Optometry at Two Notch Rd, Columbia, SC

5423050, Jun 6, 1995

Sep 23, 1994

8/311846

Mark A. Taylor - Columbia SC
Chris A. Harrison - Lexington SC
David L. Simpson - West Columbia SC
Larry C. James - West Columbia SC

NCR Corporation - Dayton OH

G06F 1100

395575

Intermodule testing in a computer system including a plurality of modules interconnected via a system bus is performed by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct the modules of the computer system. Intermodule test data is maintained in memory on each of the modules and is accessible through operations of the serial test bus. Intermodule test data is retrieved by the serial test bus and used to set up the modules so that one module drives the system bus with test signals defined by test vectors included within the intermodule test data. The remaining modules are set up to receive the test signals. Tables are developed in accordance with the intermodule test data to define which test signals drive which system bus leads and also which receiving modules receive the test signals. The signals which are received by the modules set up to receive the test signals are sampled and compared to what signals should have been received to detect errors in intermodule communications.

5377198, Dec 27, 1994

Nov 27, 1991

7/799507

David L. Simpson - West Columbia SC
Mark A. Taylor - Columbia SC

NCR Corporation (nka AT&T Global Information Solutions Company - Dayton OH

H04B 1700

371 223

A method for detecting JTAG errors in which components in a boundary scan path of a JTAG serial test bus connect a single bit bypass register into the scan path rather than the expected register when errors are detected. JTAG instruction signals are shifted into the scan path to determine whether an instruction error was received by a component. Data scanned into the component is prefixed by a header which is monitored by the JTAG control circuitry to detect any instruction errors. The combined data and header are padded by bits preceding the header to be equal to a multiple of a data register contained within the JTAG control circuitry. The least significant bit positions of the header and the padding bits are shifted out of the data register prior to the time that the header or first byte of the header should have been in the data register of the JTAG control circuitry such that the least significant bit of the data register is a 1, if no single error occurred, and is a 0 if a single error occurred.

5325368, Jun 28, 1994

Nov 27, 1991

7/799512

Larry C. James - West Columbia SC
Mark A. Taylor - Columbia SC
Chris A. Harrison - Lexington SC
David L. Simpson - West Columbia SC

NCR Corporation - Dayton OH

G01R 3128

371 223

Nonvolatile memory is provided on each module of a computer system including one or more modules with each module including a plurality of components including JTAG technology. A test bus operable in accordance with the 1149. 1 standard is included in the computer system and is arranged to access the nonvolatile memory. Boundary scan information for the components on a module and also additional information, preferably fully describing all JTAG related characteristics and operations, is stored in the nonvolatile memory. A JTAG bus system is then able to access the module memory and obtain all information required to fully implement JTAG operations for the module.