Mark Robert Storey
Veterinary at Swallow Bnd, Fort Collins, CO
License number
Colorado 3547
Issued Date
Jun 30, 1980
Renew Date
Oct 31, 1982
Expiration Date
Oct 31, 1982
Type
Veterinarian
Address
Address
3121 Swallow Bnd, Fort Collins, CO 80525
Professional information
Hw Director, Hewlett-Packard Storage
Position:
HW Director at Hewlett-Packard
Location:
Fort Collins, Colorado Area
Industry:
Computer Hardware
Work:
Hewlett-Packard
- Fort Collins, Colorado Area since Jun 1991
-
HW Director
Education:
University of Idaho 1986 - 1991
BS, Electrical Engineering
BS, Electrical Engineering
Skills:
HP, Storage, Debugging, Firmware, Cloud Computing, Storage Area Networks, Fibre Channel, Enterprise Storage, Hardware Architecture, Storage Virtualization
Hw Director, Hewlett-Packard Storage
Position:
HW Director at Hewlett-Packard
Location:
Fort Collins, Colorado Area
Industry:
Computer Hardware
Work:
Hewlett-Packard
- Fort Collins, Colorado Area since Jun 1991
-
HW Director
Education:
University of Idaho 1986 - 1991
BS, Electrical Engineering
BS, Electrical Engineering
Simultaneous Execution Of Two Memory Reference Instructions With Only One Address Calculation
US Patent:
5829049, Oct 27, 1998
Filed:
Jan 21, 1997
Appl. No.:
8/785105
Inventors:
William L. Walker - Fort Collins CO
Mark R. Storey - Fort Collins CO
Patrick Knebel - Fort Collins CO
Stephen R. Undy - Fort Collins CO
Mark R. Storey - Fort Collins CO
Patrick Knebel - Fort Collins CO
Stephen R. Undy - Fort Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 928
US Classification:
711168
Abstract:
A method of improving the performance of a computer processor by recognizing that two consecutive register instructions can be executed simultaneously and executing the two instructions simultaneously while generating a single data address and while performing exception checking on a single data address. During an instruction fetch process, two consecutive instructions are tested to determine if both are either register load instructions or register save instructions. If both instructions are load or save register instructions, the corresponding data addresses are tested to see if both data addresses are in the same double word. If both data addresses are in the same double word, then the instructions are executed simultaneously. Only one data address generation is required and exception processing is performed on only one data address. In one example embodiment, a simplified test rapidly ensures that both data addresses are in the same double word, but also requires the base addresses to be at an even word boundary.