MARK P JOHNSON
Electrician at Ashley Way, Austin, TX

6185633, Feb 6, 2001

Mar 18, 1998

9/040585

Mark A. Johnson - Austin TX

National Semiconductor Corp. - Santa Clara CA

G06F 1300

710 22

A descriptor controlled transmit and receive scatter/gather Direct Memory Access Controller efficiently moves data frames comprised of scattered blocks of data from within memory to a destination interface via a multibyte-wide buffer. The transfer of frames into a transmit buffer and out of a receive buffer is optimized regardless of the total length of the component data blocks and regardless of whether the data blocks include an odd or even number of bytes, whether the data blocks begin at an odd or even address, or whether the data blocks are misaligned with regard to memory width boundaries. A DMAC in accordance with an embodiment of the present invention stores information provided by a descriptor before frame processing takes place. This information in conjunction with steering logic and accumulator registers is used to control the steering and storing of the frame data as it passes through the DMAC to the transmit buffer or from the receive buffer. An alternate embodiment of the present invention performs these functions based on the present values of the descriptor fields.

5758176, May 26, 1998

Sep 28, 1994

8/313970

Ramesh Chandra Agarwal - Yorktown Heights NY
Randall Dean Groves - Austin TX
Fred Gehrung Gustavson - Briarcliff Manor NY
Mark Alan Johnson - Austin TX
Brett Olsson - Round Rock TX

International Business Machines Corporation - Armonk NY

G06F 938

395800

A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.

2004022, Nov 4, 2004

May 2, 2003

10/428893

Jeffrey Aman - Poughkeepsie NY, US
David Bostjancic - Poughkeepsie NY, US
Donna Eng Dillenberger - Yorktown Heights NY, US
Gregory Dritschler - Poughkeepsie NY, US
Mark Hulber - New York NY, US
Mark Johnson - Austin TX, US
Hiren Shah - Highland NY, US
Alan Webb - Ridgefield CT, US
Peter Yocom - LaGrangeville NY, US

International Business Machines Corporation - Armonk NY

G06F007/00

707/100000

Workload reporting is provided in a distributed transaction processing environment having call trees in which a child application performs a child transaction on behalf of a parent application performing a parent transaction. When a parent application starts a transaction, it makes a call to a reporting agent, passing to it any parent correlator the parent application may have received from a calling application. The reporting agent returns to the parent application a child correlator, which the parent application passes to any child application it calls to perform child transactions. The child correlator contains end-to-end information classifying the parent transaction as well as a hop count indicating the depth of the child application in the call tree. The reporting agent uses the hop count to construct a topology in which commonly classified applications are grouped according to their depth in the call tree for better visualization of performance of individual applications.

5887183, Mar 23, 1999

Jan 4, 1995

8/368173

Ramesh Chandra Agarwal - Yorktown Heights NY
Randall Dean Groves - Austin TX
Fred G. Gustavson - Briarcliff Manor NY
Mark A. Johnson - Austin TX
Terry L. Lyon - Fort Collins CO
Brett Olsson - Round Rock TX
James B. Shearer - Ossining NY

International Business Machines Corporation - Armonk NY

G06F 1580

39580002

A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.

5825677, Oct 20, 1998

Mar 20, 1996

8/619456

Ramesh Chandra Agarwal - Yorktown Heights NY
Randall Dean Groves - Austin TX
Fred Gehrung Gustavson - Briarcliff Manor NY
Mark Alan Johnson - Austin TX
Brett Olsson - Round Rock TX

International Business Machines Corporation - Armonk NY

G06F 1716

36473603

A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.